公开(公告)号：US20180342589A1

公开(公告)日：2018-11-29

申请号：US15966773

申请日：2018-04-30

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Tatsuo NAKAYAWA ,  Yasuhiro OKAMOTO ,  Atsushi TSUBOI

IPC: H01L29/20 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L29/2003 ,  H01L21/0262 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/4232 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/432 ,  H01L29/513 ,  H01L29/66462 ,  H01L29/7783

Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.

公开(公告)号：US20180026099A1

公开(公告)日：2018-01-25

申请号：US15604848

申请日：2017-05-25

Applicant: Renesas Electronics Corporation

Inventor： Hironobu MIYAMOTO ,  Tatsuo NAKAYAMA ,  Atsushi TSUBOI ,  Yasuhiro OKAMOTO ,  Hiroshi KAWAGUCHI

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/423 ,  H01L23/528 ,  H01L23/522 ,  H01L29/778 ,  H01L29/205

CPC classification number: H01L29/1087 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787

Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.