公开(公告)号：US20180053658A1

公开(公告)日：2018-02-22

申请号：US15796621

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Kentaro SAITO ,  Hideki SUGIYAMA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA

IPC: H01L21/28 ,  H01L29/792 ,  H01L29/66 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L21/28282 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/60 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

公开(公告)号：US20230282745A1

公开(公告)日：2023-09-07

申请号：US17686042

申请日：2022-03-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki SUGIYAMA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L29/7836 ,  H01L29/0847 ,  H01L29/6659 ,  H01L21/26513 ,  H01L21/266

Abstract: Semiconductor device includes a well region formed in an active region of a semiconductor substrate, a gate electrode formed on the well region via a gate dielectric film, and a source region and a drain region formed in the well region. At the vicinity of both end portions of the active region in the first direction, a first region and a second region having the same conductivity type as the well region and having impurity concentration higher than that of the well region are formed in the well region. The first region and the second region are spaced from each other in a second direction perpendicular to the first direction, and at least a portion of each of them is located under the gate electrode. The first region and the second region are not formed at the center portion of the active region in the first direction.

公开(公告)号：US20170053922A1

公开(公告)日：2017-02-23

申请号：US15236472

申请日：2016-08-14

Applicant: Renesas Electronics Corporation

Inventor： Kentaro SAITO ,  Hideki SUGIYAMA ,  Hiraku CHAKIHARA ,  Yoshiyuki KAWASHIMA

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792

CPC classification number: H01L21/28282 ,  H01L27/0629 ,  H01L27/11573 ,  H01L28/60 ,  H01L29/66833 ,  H01L29/792

Abstract: In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.

Abstract translation: 在半导体器件中，存储单元由彼此相邻的控制栅电极和存储栅电极形成，形成在控制栅电极下方的栅绝缘膜和形成在存储栅电极下方并具有电荷累积的绝缘膜 其中的部分。 此外，在该半导体器件中，电容元件由形成在上电极和下电极之间的下电极，上电极和电容绝缘膜形成。 下电极的厚度小于控制栅电极的厚度。