公开(公告)号：US20190181888A1

公开(公告)日：2019-06-13

申请号：US16154459

申请日：2018-10-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Wataru NAITO ,  Noriyoshi IZUMI ,  Kazuhiro KIJIMA

IPC: H04B1/00 ,  H04B1/10 ,  H03D7/16 ,  H03D3/00 ,  H03H19/00 ,  H04B1/30 ,  H04B1/403

Abstract: An IF filter band-limits an intermediate frequency signal outputted from a mixer. An AFC unit controls the oscillation frequency of a PLL so that the frequency of the intermediate frequency signal is a predetermined frequency. When the AFC unit controls the oscillation frequency of the PLL, a band control unit controls the passing characteristic of the IF filter to the passing characteristic of a wide band, and after the completion of the control, controls the passing characteristic of the IF filter to the passing characteristic of a narrow band. A frequency correction unit refers to a filter information storage unit, and corrects the oscillation frequency controlled by the AFC unit according to the difference between the center frequency of the passband of the passing characteristic of the wide band and the center frequency of the passband of the passing characteristic of the narrow band.

公开(公告)号：US20170094596A1

公开(公告)日：2017-03-30

申请号：US15232152

申请日：2016-08-09

Applicant: Renesas Electronics Corporation

Inventor： Kazuhiro KIJIMA ,  Wataru NAITO

IPC: H04W52/02 ,  H03L7/185 ,  H04B1/16

CPC classification number: H04W52/0209 ,  H03L7/185 ,  H04B1/16 ,  H04W52/0261 ,  Y02D70/00

Abstract: According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.

公开(公告)号：US20180049119A1

公开(公告)日：2018-02-15

申请号：US15792880

申请日：2017-10-25

Applicant: Renesas Electronics Corporation

Inventor： Kazuhiro KIJIMA ,  Wataru NAITO

IPC: H04W52/02 ,  H04B1/16 ,  H03L7/185

CPC classification number: H04W52/0209 ,  H03L7/185 ,  H04B1/16 ,  H04W52/0261 ,  Y02D70/00

Abstract: According to one embodiment, a radio communication device 1 includes a variable frequency divider 17 that divides a frequency of a reference clock REFCLK and outputs a frequency divided clock DCLK; a controller 15 that controls a frequency dividing ratio of the variable frequency divider 17 so that an integral multiple of a frequency of the frequency divided clock DCLK is not included in a frequency band of a high-frequency signal that has been received from outside by radio; and a DCDC converter 18 that performs a switching operation in synchronization with the frequency divided clock DCLK to generate an output voltage Vout obtained by stepping down an input voltage Vin.

公开(公告)号：US20170085270A1

公开(公告)日：2017-03-23

申请号：US15224368

申请日：2016-07-29

Applicant: Renesas Electronics Corporation

Inventor： Hidehiko SUZUKI ,  Naoki KOIZUMI ,  Hisaya ISHIHARA ,  Kazuhiro KIJIMA

IPC: H03L1/02 ,  H03L7/089 ,  H03B5/12 ,  H03B5/32

CPC classification number: H03L1/026 ,  H03B5/04 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1278 ,  H03B5/32 ,  H03B2200/004 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/10 ,  H03L7/181 ,  H03L7/23

Abstract: An object is to avoid a deadlock in a PLL. A PLL synthesizer includes a PLL circuit that includes a voltage control oscillation circuit configured to control an oscillation frequency according to a control voltage, an oscillation frequency storage unit configured to previously store the oscillation frequency at a first temperature, a control voltage setting unit configured to set a control voltage based on a difference between the oscillation frequency at a second temperature and the stored oscillation frequency, and a calibration processing unit configured to calibrate the voltage control oscillation circuit in a state in which the control voltage is set so that the oscillation frequency will become a predetermined frequency.