公开(公告)号：US20160077909A1

公开(公告)日：2016-03-17

申请号：US14953403

申请日：2015-11-29

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki FURUYA ,  Osamu WATANABE ,  Satoshi KONDO

IPC: G06F11/07

CPC classification number: G06F11/0757 ,  G06F1/24 ,  G06F1/3203 ,  G06F1/3234 ,  G06F11/0721 ,  G06F11/079 ,  Y02D50/20

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

公开(公告)号：US20180032391A1

公开(公告)日：2018-02-01

申请号：US15711000

申请日：2017-09-21

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki FURUYA ,  Osamu WATANABE ,  Satoshi KONDO

IPC: G06F11/07 ,  G06F1/24 ,  G06F1/32

CPC classification number: G06F11/0757 ,  G06F1/24 ,  G06F1/3203 ,  G06F1/3234 ,  G06F11/0721 ,  G06F11/079 ,  Y02D50/20

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

公开(公告)号：US20130198539A1

公开(公告)日：2013-08-01

申请号：US13754982

申请日：2013-01-31

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki FURUYA ,  Osamu WATANABE ,  Satoshi KONDO

IPC: G06F1/32

CPC classification number: G06F11/0757 ,  G06F1/24 ,  G06F1/3203 ,  G06F1/3234 ,  G06F11/0721 ,  G06F11/079 ,  Y02D50/20

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract translation: 公开了一种用于微机监控系统的看门狗定时器电路。 该电路包括响应于接收到用于对其进行计数的计数时钟信号的定时器电路，以及定时器控制电路，其与定时器刷新指令（prun）同步地加载外部输入的数据信号（stn），并且在其中保持顺序加载 最新的多位数据信号作为参考数据。 当参考数据与预定义模式一致时，同时满足另一个预定条件时，定时器控制电路中断定时器电路的时钟信号计数操作。 在计数操作中断期间，当参考数据与预定义模式不一致时，或者当上述另一个预定条件不满足时，控制电路允许定时器电路重启时钟信号计数操作。