-
公开(公告)号：US10396549B2
公开(公告)日：2019-08-27
申请号：US15918309
申请日：2018-03-12
发明人： Masashi Arakawa , Tadashi Fukui , Koji Takayanagi
摘要： Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.
-
公开(公告)号：US09948090B2
公开(公告)日：2018-04-17
申请号：US14865418
申请日：2015-09-25
发明人： Masashi Arakawa , Tadashi Fukui , Koji Takayanagi
CPC分类号： H02H9/044 , H01L27/0285 , H02H9/005
摘要： Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.
-
搜索结果
2 条记录 (耗时 0.014 秒)
