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    Semiconductor device and a method increasing a resistance value of an electric fuse
    1.
    发明授权
    Semiconductor device and a method increasing a resistance value of an electric fuse 有权
    半导体器件和增加电熔丝的电阻值的方法

    公开(公告)号：US09508641B2

    公开(公告)日：2016-11-29

    申请号：US14590294

    申请日：2015-01-06

    申请人： Renesas Electronics Corporation

    发明人： Takeshi Iwamoto ,  Kazushi Kono ,  Masashi Arakawa ,  Toshiaki Yonezu ,  Shigeki Obayashi

    IPC分类号： H01L23/525 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L23/62

    CPC分类号： H01L23/5256 ,  H01H85/041 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

    摘要翻译： 一种具有电熔丝结构的半导体器件，其接收电流以允许电熔丝被切割而不损坏保险丝周围的部分。 电熔丝可以电连接在电子电路和冗余电路之间作为电子电路的备用电路。 在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。 电熔丝形成为细层，由主配线和阻挡膜构成。 主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。 主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。

    SEMICONDUCTOR DEVICE AND A METHOD OF INCREASING A RESISTANCE VALUE OF AN ELECTRIC FUSE
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND A METHOD OF INCREASING A RESISTANCE VALUE OF AN ELECTRIC FUSE 审中-公开
    半导体器件和增加电熔丝电阻值的方法

    公开(公告)号：US20140021559A1

    公开(公告)日：2014-01-23

    申请号：US14033036

    申请日：2013-09-20

    申请人： Renesas Electronics Corporation

    发明人： Takeshi IWAMOTO ,  Kazushi Kono ,  Masashi Arakawa ,  Toshiaki Yonezu ,  Shigeki Obayashi

    IPC分类号： H01L23/525

    CPC分类号： H01L23/5256 ,  H01H85/041 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is a semiconductor device having an electric fuse structure which receives the supply of an electric current to be permitted to be cut without damaging portions around the fuse. An electric fuse is electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the supply of an electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

    摘要翻译： 提供一种具有电熔丝结构的半导体器件，其接收要被允许切割的电流的供应，而不损坏保险丝周围的部分。 电子熔断器电连接在电子电路和冗余电路之间，作为电子电路的备用电路。 在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。 电熔丝形成为细层，由主配线和阻挡膜构成。 主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。 主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10396549B2

    公开(公告)日：2019-08-27

    申请号：US15918309

    申请日：2018-03-12

    申请人： Renesas Electronics Corporation

    发明人： Masashi Arakawa ,  Tadashi Fukui ,  Koji Takayanagi

    IPC分类号： H02H9/00 ,  H02H9/04 ,  H01L27/02

    摘要： Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.

    Semiconductor integrated circuit device
    5.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US09214217B2

    公开(公告)日：2015-12-15

    申请号：US14450247

    申请日：2014-08-03

    申请人： Renesas Electronics Corporation

    发明人： Natsuki Ikehata ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

    IPC分类号： H03F3/45 ,  G11C11/4076 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4091

    CPC分类号： G11C11/4091 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

    摘要翻译： 差分放大电路的输出信号特性得到改善。 当输入数据信号为“低”时，流过第一晶体管的电流将减小，并且第一电阻和第二电阻之间的连接（节点）的电位将增加。 该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。 当输入数据信号为“高”时，第一晶体管的电流增加，因此节点处的电位减小。 因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。 因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    6.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20140334240A1

    公开(公告)日：2014-11-13

    申请号：US14450247

    申请日：2014-08-03

    申请人： Renesas Electronics Corporation

    发明人： Natsuki Ikehata ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

    IPC分类号： G11C11/4076 ,  G11C11/4091

    CPC分类号： G11C11/4091 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

    摘要翻译： 差分放大电路的输出信号特性得到改善。 当输入数据信号为“低”时，流过第一晶体管的电流将减小，并且第一电阻和第二电阻之间的连接（节点）的电位将增加。 该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。 当输入数据信号为“高”时，第一晶体管的电流增加，因此节点处的电位减小。 因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。 因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09948090B2

    公开(公告)日：2018-04-17

    申请号：US14865418

    申请日：2015-09-25

    申请人： Renesas Electronics Corporation

    发明人： Masashi Arakawa ,  Tadashi Fukui ,  Koji Takayanagi

    IPC分类号： H02H9/00 ,  H02H9/04 ,  H01L27/02

    CPC分类号： H02H9/044 ,  H01L27/0285 ,  H02H9/005

    摘要： Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.