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1.发明授权Integrated processing unit, particularly for connected speech recognition systems 失效综合处理单元，特别是连接语音识别系统
公开(公告)号：US4907278A
公开(公告)日：1990-03-06
申请号：US211812
申请日：1988-06-27
申请人： Riccardo Cecinati , Alberto Ciaramella , Luigi Licciardi , Maurizio Paolini , Robert Tasso , Giovanni Venuti
发明人： Riccardo Cecinati , Alberto Ciaramella , Luigi Licciardi , Maurizio Paolini , Robert Tasso , Giovanni Venuti
IPC分类号： C07D209/54 , A61K31/415 , A61K31/4184 , A61K31/557 , A61P1/04 , C07C27/00 , C07C29/143 , C07C35/06 , C07C45/00 , C07C47/192 , C07C51/00 , C07C59/11 , C07C59/353 , C07C67/00 , C07C69/67 , C07C69/675 , C07C69/716 , C07C209/00 , C07C209/26 , C07C213/00 , C07C227/00 , C07C227/08 , C07C239/00 , C07C241/00 , C07C243/20 , C07C247/06 , C07C247/12 , C07C247/14 , C07C253/00 , C07C255/31 , C07D235/02 , G10L15/00 , G10L15/12 , G10L15/14
摘要： This connected-speech recognition system uses a two-level hierarchical system, in which the higher-level (master) processor and one or more lower-level units (slaves) process, respectively, the most probably word sequence within a permitted grammar network, and the likelihood of individual words with the grammar network. The lower-level processing performs dynamic programming involving vector and matrix calculation and comparison, and processing speed is improved by an integrated processing unit which has simultaneous access to the external data memory as well as to a high-speed internal microinstruction ROM. One of the aforementioned units can also provide for performing an additional internal test function. The structure features two internal data buses and internal memories for more commonly used data and addresses, for enabling high-speed microinstruction performance and external memory access. The external memory is divided into tables differing structurally but such as to be accessed in uniform manner by the internal addressing unit.
摘要翻译： 该连接语音识别系统使用两级分层系统，其中较高级（主）处理器和一个或多个较低级单元（从站）分别处理允许的语法网络中最可能的字序列， 以及单词与语法网络的可能性。 下级处理执行涉及向量和矩阵计算和比较的动态规划，并且通过具有同时访问外部数据存储器以及高速内部微指令ROM的集成处理单元改进处理速度。 上述单元之一也可以提供执行额外的内部测试功能。 该结构具有两个内部数据总线和内部存储器，用于更常用的数据和地址，以实现高速微指令性能和外部存储器访问。 外部存储器被分成在结构上不同但是由内部寻址单元以均匀方式访问的表格。
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公开(公告)号：US5907641A
公开(公告)日：1999-05-25
申请号：US728310
申请日：1996-10-09
CPC分类号： G06K9/6203
摘要： A system for comparing digital images, whereby a first and second data processing block receive respective data streams corresponding to a reference image and a detected image for comparison with the reference image. The data processing blocks detect reference points in the images, and generate data, which is supplied to a block for determining a first approximation of the function A.sub.o relating the two images. The system also presents blocks for successively refining the function relating the reference image to the detected image. (FIG. 1)
摘要翻译： 一种用于比较数字图像的系统，由此第一和第二数据处理块接收与参考图像相对应的相应数据流和用于与参考图像进行比较的检测图像。 数据处理块检测图像中的参考点，并产生数据，该数据被提供给用于确定关于两个图像的函数Ao的第一近似的块。 该系统还提供用于连续地将与参考图像相关的功能精细化的检测图像的块。 （图。1）
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公开(公告)号：US5787200A
公开(公告)日：1998-07-28
申请号：US537282
申请日：1995-09-29
CPC分类号： G06K9/6202
摘要： A SLAVE coprocessor connectable to a MASTER processor and cooperating with at least one external memory. The coprocessor presents an internal memory communicating with an internal data line extending between a first and second interface circuit communicating respectively with the processor and the external memory; the internal memory contains a character composed of a rectangular matrix of pixels corresponding to a digitized alphanumeric character; and the coprocessor presents an electronic arithmetic unit for comparing a character from the internal memory with a reference matrix from the external memory.
摘要翻译： 可以连接到MASTER处理器并与至少一个外部存储器配合的SLAVE协处理器。 协处理器呈现与内部数据线通信的内部存储器，该内部数据线在分别与处理器和外部存储器通信的第一和第二接口电路之间延伸; 内部存储器包含由与数字化的字母数字字符相对应的像素的矩形矩阵组成的字符; 并且协处理器呈现用于将来自内部存储器的字符与来自外部存储器的参考矩阵进行比较的电子运算单元。
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