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1.发明授权
公开(公告)号：US4133030A
公开(公告)日：1979-01-02
申请号：US760773
申请日：1977-01-19
申请人： Robert E. Huettner , John P. Grandmaison , John H. Vernon , Richard A. Lemay , Edward Beauchemin
发明人： Robert E. Huettner , John P. Grandmaison , John H. Vernon , Richard A. Lemay , Edward Beauchemin
CPC分类号： G06F13/385 , G06F13/122
摘要： Data is transferred between a main memory in a data processing system and communication channels under the control of communications control blocks provided in an auxiliary memory, each of which control blocks includes a starting address, range and status information so as to enable the transfer of data to data blocks included in the main memory as indicated by the starting address in the control blocks. A predetermined number of control blocks is allocated in the auxiliary memory for each communications channel and the transfer of all such data is performed utilizing as many of the predetermined number of control blocks as required for the channel until the transfer is complete as indicated by the last such control block utilized in the transfer. Control blocks are loaded in the auxiliary memory under control of the central processor of the system and are periodically accessed by the processor to determine the status of data transfer operations. Circuits are provided for preventing the loading in the auxiliary memory of more than the predetermined number of control blocks for a channel and for preventing the execution of a status inquiry for a channel when no control blocks for that channel are in the active state.
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2.发明授权Communications processor employing line-dedicated memory tables for supervising data transfers 失效通信处理器采用行专用存储表来监控数据传输
公开(公告)号：US4261033A
公开(公告)日：1981-04-07
申请号：US760782
申请日：1977-01-19
CPC分类号： G06F13/34 , G06F13/385
摘要： A communications processor is coupled between a main memory and a plurality of communications channels and with a central processing unit and includes control mechanisms for processing the transfer of information between the processor and the main memory with minimum interruption of the central processing unit. The processor further includes control tables and a plurality of control routines enabling the processing of the transfer of the information between the processor and the channels. The routines are unique to the communications channel characteristics of the device coupled with the channel being serviced and is configurable to reflect any changes made in such characteristics.
摘要翻译： 通信处理器耦合在主存储器和多个通信信道之间并且与中央处理单元相连，并且包括用于在中央处理单元的中断最小的情况下处理处理器和主存储器之间的信息传送的控制机制。 处理器还包括控制表和多个控制例程，使得能够处理处理器和通道之间的信息传送。 这些例程对于与被维护的信道耦合的设备的通信信道特性是唯一的，并且可配置为反映在这些特性中所做的任何改变。
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3.发明授权Communication line service interrupt technique for a communications processing system 失效通信线路业务中断技术，用于通信处理系统
公开(公告)号：US4348725A
公开(公告)日：1982-09-07
申请号：US760772
申请日：1977-01-19
申请人： Robert J. Farrell , Kenneth T. Coit , John H. Vernon , Kin C. Yu , Robert E. Huettner , John P. Grandmaison
发明人： Robert J. Farrell , Kenneth T. Coit , John H. Vernon , Kin C. Yu , Robert E. Huettner , John P. Grandmaison
CPC分类号： G06F9/4812 , G06F13/124 , G06F13/34
摘要： A programmable communications processor is coupled to execute instructions of programs designed to process the transfer of information between a plurality of communication channels and a main memory included in the system. A software implemented and controlled pause counter enables the execution of a given maximum number of instructions for servicing, for example, a communication channel following which it suspends or pauses such servicing, in order to service another higher priority request which may be pending. Processing of lower priority service requests thus cannot delay the recognition and handling of higher priority requests for more than a minimum period of time and the effective throughput rate is increased.
摘要翻译： 可编程通信处理器被耦合以执行旨在处理多个通信信道与系统中包括的主存储器之间的信息传送的程序的指令。 软件实现和控制的暂停计数器使得能够执行用于服务的给定最大数量的指令，例如，其挂起或暂停此类服务的通信信道，以便服务可能正在等待的另一较高优先级请求。 因此，较低优先级服务请求的处理不能延迟对较高优先级请求的识别和处理超过最小时间段，并且有效吞吐率增加。
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4.发明授权Communication line status scan technique for a communications processing system 失效通信处理系统的通信线路状态扫描技术
公开(公告)号：US4336588A
公开(公告)日：1982-06-22
申请号：US760784
申请日：1977-01-19
CPC分类号： G06F13/26 , G06F13/126
摘要： A communication processor is coupled to recognize and handle on a priority basis, service interrupt requests from a plurality of communication line adapters. The processor is also adapted to perform a firmware-controlled scan of the communication line adapters, completely independently of any data transfers involving such adapters, to determine the status of the communication lines handled thereby and, on detection of a status which is changed from a previously stored status, to store the new status in the processor and take any action necessary as indicated by a command previously stored in the processor.
摘要翻译： 耦合通信处理器以优先级识别和处理来自多个通信线适配器的服务中断请求。 处理器还适于完全独立于涉及这种适配器的任何数据传输来执行通信线路适配器的固件控制的扫描，以确定由此处理的通信线路的状态，并且在检测到从 先前存储的状态，以将新状态存储在处理器中，并采取必要的任何操作，如先前存储在处理器中的命令所指示的。
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5.发明授权
公开(公告)号：US4325119A
公开(公告)日：1982-04-13
申请号：US760783
申请日：1977-01-19
CPC分类号： G06F9/226 , G06F13/32 , G06F13/385
摘要： Firmware generated commands provided by a control store in a microprogrammed communications processor which is coupled in a system including a main memory and a central processing unit control the processing of instructions from the central processing unit, interrupts from the communications channels and servicing of such channels if a channel status change is detected. The firmware also controls the operation of the servicing of such channels by providing a control mechanism by which data is read from or written into the main memory. Further, interrupts which are not handled immediately are handled in a deferred interrupt arrangement.
摘要翻译： 由微控制通信处理器中的控制存储器提供的固件生成命令，其耦合在包括主存储器和中央处理单元的系统中，控制来自中央处理单元的指令的处理，来自通信信道的中断以及对这些通道的服务，如果 检测到通道状态变化。 固件还通过提供从主存储器读取或写入数据的控制机制来控制对这些通道的操作。 此外，不是立即处理的中断在延迟中断安排中被处理。
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