公开(公告)号：US20220138133A1

公开(公告)日：2022-05-05

申请号：US17462975

申请日：2021-08-31

申请人： Intel Corporation

发明人： Gilbert Neiger ,  Rajesh M. Sankaran

IPC分类号： G06F13/34

摘要： Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

公开(公告)号：US11113217B2

公开(公告)日：2021-09-07

申请号：US16778227

申请日：2020-01-31

申请人： Intel Corporation

发明人： Gilbert Neiger ,  Rajesh M. Sankaran

IPC分类号： G06F13/34

摘要： Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

公开(公告)号：US10572415B2

公开(公告)日：2020-02-25

申请号：US15900771

申请日：2018-02-20

申请人： Intel Corporation

发明人： Gilbert Neiger ,  Rajesh M. Sankaran

IPC分类号： G06F13/00 ,  G06F13/34

摘要： Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

公开(公告)号：US10558597B2

公开(公告)日：2020-02-11

申请号：US15683907

申请日：2017-08-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jeongwoo Park

IPC分类号： G06F13/362 ,  G06F13/24 ,  G06F13/28 ,  G06F13/18 ,  G06F13/34

摘要： An application processor includes: a plurality of interrupt sources to which a plurality of interrupt numbers are respectively assigned; a Central Processing Unit (CPU) configured to receive an interrupt request signal and an interrupt number signal and perform an interrupt handling process for at least one of the plurality of interrupt sources, the at least one of the plurality of interrupt sources corresponding to the interrupt number signal; and an interrupt controller including a master interface connected to a system bus, the interrupt controller being configured to generate the interrupt request signal and the interrupt number signal based on an interrupt signal, which is received from the at least one of the plurality of interrupt sources, and to transmit the interrupt number signal to the CPU via the master interface.

公开(公告)号：US10114776B2

公开(公告)日：2018-10-30

申请号：US15498846

申请日：2017-04-27

申请人： Microchip Technology Incorporated

发明人： Sean Steedman ,  Kevin Kilzer ,  Ashish Senapati ,  Justin Milks ,  Prashanth Pulipaka

IPC分类号： G06F13/36 ,  G06F13/00 ,  G06F13/362 ,  G06F13/26 ,  G06F13/28 ,  G06F13/40 ,  G06F13/34

摘要： A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

公开(公告)号：US10055369B1

公开(公告)日：2018-08-21

申请号：US15470643

申请日：2017-03-27

申请人： Apple Inc.

发明人： Charles E. Tucker ,  Erik P. Machnicki ,  Fan Wu ,  John H. Kelm

IPC分类号： G06F13/26 ,  G06F13/34 ,  H04L12/46 ,  G06F9/48 ,  H04L12/801 ,  G06F9/50

CPC分类号： G06F13/26 ,  G06F9/4812 ,  G06F9/4825 ,  G06F9/4843 ,  G06F9/5038 ,  G06F13/34 ,  H04L12/46 ,  H04L47/29 ,  Y02D10/14

摘要： Systems, apparatuses, and methods for coalescing interrupts temporally for later processing are described. An interrupt controller in a computing system maintains a timer for tracking an amount of time remaining after receiving an interrupt before a processor is awakened to service the interrupt. For a received interrupt with a latency tolerance greater than a threshold, the interrupt controller compares a value currently stored in the timer and the latency tolerance selected based on class. The smaller value is retained in the timer. When the timer expires, the interrupt controller sends wakeup indications to one or more processors and indications of the waiting interrupts.

公开(公告)号：US20170180315A1

公开(公告)日：2017-06-22

申请号：US15454887

申请日：2017-03-09

申请人： Fortinet, Inc.

发明人： Zhiwei Dai ,  Xu Zhou

IPC分类号： H04L29/06 ,  H04L12/26 ,  G06F13/34 ,  G06F9/48 ,  G06F15/78

CPC分类号： H04L63/0209 ,  G06F9/4887 ,  G06F13/1673 ,  G06F13/225 ,  G06F13/28 ,  G06F13/34 ,  G06F15/7825 ,  G06F2213/2408 ,  G06F2213/2804 ,  H04L43/08 ,  H04L43/16 ,  H04L63/0272

摘要： Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network security device through a bus. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are delivered or make available to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing the delivery or making available of the received data packets to the host CPU for processing.

公开(公告)号：US09684617B2

公开(公告)日：2017-06-20

申请号：US14780918

申请日：2013-05-16

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Hiroyuki Iida

IPC分类号： G06F13/00 ,  G06F13/34 ,  G06F13/24 ,  G06F13/42

CPC分类号： G06F13/34 ,  G06F13/24 ,  G06F13/4282

摘要： A relaying device, when having received an interrupt notification 151 from an I/O device, transmits an interrupt factor read request 159(1) for an interrupt factor to the I/O device, based on an address information memory table 1041, without waiting for a response from a CPU, and transmits the interrupt notification 151 received, to the CPU. When having received an interrupt factor 160(1), the relaying device transmits an intra-I/O-device data read request 159(2) to the I/O device, based on an intra-I/O-device data read address storing table 1081, without waiting for a response from the CPU.

公开(公告)号：US20160179721A1

公开(公告)日：2016-06-23

申请号：US14581677

申请日：2014-12-23

申请人： Intel Corporation

发明人： GILBERT NEIGER ,  RAJESH M. SANKARAN

IPC分类号： G06F13/34

CPC分类号： G06F13/34

摘要： Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

摘要翻译： 将中断传送到用户级应用程序的系统和方法。 一个示例性处理系统包括：存储器，被配置为存储多个用户级APIC数据结构以及与由处理系统执行的多个用户级应用相对应的多个用户级中断处理程序地址数据结构; 以及处理核心，其被配置为响应于接收到用户级别中断的通知，以：在与用户级中断相关联的用户级APIC数据结构中设置具有由用户级别中断的标识符定义的位置的待决中断位标志 当前由处理核心执行的用户级应用程序，并且调用由与用户级应用程序相关联的用户级中断处理程序地址数据结构标识的用户级中断处理程序，用于具有 由用户级APIC数据结构识别的一个或多个未决用户级中断中的最高优先级。

公开(公告)号：US20150212956A1

公开(公告)日：2015-07-30

申请号：US14167497

申请日：2014-01-29

申请人： Red Hat Israel, Ltd.

发明人： Michael Tsirkin ,  Henri Han van Riel

IPC分类号： G06F13/34

CPC分类号： G06F13/34 ,  G06F9/4812 ,  G06F9/5027 ,  G06F9/5077 ,  G06F2213/2424

摘要： Systems and methods for directly updating the virtual machine memory by interrupt handlers. An example method may comprise: receiving, by a computer system, an interrupt triggered by a physical device; receiving, by an interrupt handling routine, a data frame from the physical device; identifying a virtual machine to receive the interrupt; and responsive to determining that an active memory context on the computer system matches a memory context of the virtual machine, writing, by the interrupt handling routine, the data frame into a memory of the virtual machine.

摘要翻译： 通过中断处理程序直接更新虚拟机内存的系统和方法。 示例性方法可以包括：由计算机系统接收由物理设备触发的中断; 通过中断处理例程从物理设备接收数据帧; 识别虚拟机以接收中断; 并且响应于确定所述计算机系统上的活动存储器上下文与所述虚拟机的存储器上下文匹配，通过所述中断处理例程将所述数据帧写入所述虚拟机的存储器。