公开(公告)号：US10055369B1

公开(公告)日：2018-08-21

申请号：US15470643

申请日：2017-03-27

申请人： Apple Inc.

发明人： Charles E. Tucker ,  Erik P. Machnicki ,  Fan Wu ,  John H. Kelm

IPC分类号： G06F13/26 ,  G06F13/34 ,  H04L12/46 ,  G06F9/48 ,  H04L12/801 ,  G06F9/50

CPC分类号： G06F13/26 ,  G06F9/4812 ,  G06F9/4825 ,  G06F9/4843 ,  G06F9/5038 ,  G06F13/34 ,  H04L12/46 ,  H04L47/29 ,  Y02D10/14

摘要： Systems, apparatuses, and methods for coalescing interrupts temporally for later processing are described. An interrupt controller in a computing system maintains a timer for tracking an amount of time remaining after receiving an interrupt before a processor is awakened to service the interrupt. For a received interrupt with a latency tolerance greater than a threshold, the interrupt controller compares a value currently stored in the timer and the latency tolerance selected based on class. The smaller value is retained in the timer. When the timer expires, the interrupt controller sends wakeup indications to one or more processors and indications of the waiting interrupts.

公开(公告)号：US20170180315A1

公开(公告)日：2017-06-22

申请号：US15454887

申请日：2017-03-09

申请人： Fortinet, Inc.

发明人： Zhiwei Dai ,  Xu Zhou

IPC分类号： H04L29/06 ,  H04L12/26 ,  G06F13/34 ,  G06F9/48 ,  G06F15/78

CPC分类号： H04L63/0209 ,  G06F9/4887 ,  G06F13/1673 ,  G06F13/225 ,  G06F13/28 ,  G06F13/34 ,  G06F15/7825 ,  G06F2213/2408 ,  G06F2213/2804 ,  H04L43/08 ,  H04L43/16 ,  H04L63/0272

摘要： Systems and methods for limiting the rate of packet transmission from a NIC to a host CPU are provided. According to one embodiment, data packets are received from a network by the NIC. The NIC is coupled to a host central processing unit (CPU) of a network security device through a bus. A status of the host CPU is monitored by the NIC. A rate limiting mode indicator is set by the NIC based on the status. When the rate limiting mode indicator indicates rate limiting is inactive, then the received data packets are delivered or make available to the host CPU for processing. When the rate limiting mode indicator indicates rate limiting is active, then rate limiting is performing by temporarily stopping or slowing the delivery or making available of the received data packets to the host CPU for processing.

公开(公告)号：US09684617B2

公开(公告)日：2017-06-20

申请号：US14780918

申请日：2013-05-16

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Hiroyuki Iida

IPC分类号： G06F13/00 ,  G06F13/34 ,  G06F13/24 ,  G06F13/42

CPC分类号： G06F13/34 ,  G06F13/24 ,  G06F13/4282

摘要： A relaying device, when having received an interrupt notification 151 from an I/O device, transmits an interrupt factor read request 159(1) for an interrupt factor to the I/O device, based on an address information memory table 1041, without waiting for a response from a CPU, and transmits the interrupt notification 151 received, to the CPU. When having received an interrupt factor 160(1), the relaying device transmits an intra-I/O-device data read request 159(2) to the I/O device, based on an intra-I/O-device data read address storing table 1081, without waiting for a response from the CPU.

公开(公告)号：US20160179721A1

公开(公告)日：2016-06-23

申请号：US14581677

申请日：2014-12-23

申请人： Intel Corporation

发明人： GILBERT NEIGER ,  RAJESH M. SANKARAN

IPC分类号： G06F13/34

CPC分类号： G06F13/34

摘要： Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

摘要翻译： 将中断传送到用户级应用程序的系统和方法。 一个示例性处理系统包括：存储器，被配置为存储多个用户级APIC数据结构以及与由处理系统执行的多个用户级应用相对应的多个用户级中断处理程序地址数据结构; 以及处理核心，其被配置为响应于接收到用户级别中断的通知，以：在与用户级中断相关联的用户级APIC数据结构中设置具有由用户级别中断的标识符定义的位置的待决中断位标志 当前由处理核心执行的用户级应用程序，并且调用由与用户级应用程序相关联的用户级中断处理程序地址数据结构标识的用户级中断处理程序，用于具有 由用户级APIC数据结构识别的一个或多个未决用户级中断中的最高优先级。

公开(公告)号：US20150347592A1

公开(公告)日：2015-12-03

申请号：US14294710

申请日：2014-06-03

申请人： International Business Machines Corporation

发明人： Alper Buyuktosunoglu ,  Srivatsan Chellappa ,  Toshiaki Kirihata ,  Karthik V. Swaminathan

IPC分类号： G06F17/30 ,  G06F12/08

CPC分类号： G06F17/30424 ,  G06F12/0897 ,  G06F13/1626 ,  G06F13/1663 ,  G06F13/34 ,  G06F13/374 ,  G06F17/30312 ,  G06F17/3053 ,  G06F17/30867 ,  G06F2212/154

摘要： A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order.

摘要翻译： 本地排序模块包括一组存储二进制向量的存储元素，二进制向量被配置为一维（2D）或二维（2D）阵列结构，并且被相应的比较器分隔，用于有条件地比较和分类二进制向量。 比较器可以使用比较和翻转或比较和交换操作来执行排序。 本地排序模块可以与全局排序模块耦合，以使比赛排序算法能够一次输出存储在存储元件中的值，直到以预定排序顺序输出所有数据。

公开(公告)号：US20150212956A1

公开(公告)日：2015-07-30

申请号：US14167497

申请日：2014-01-29

申请人： Red Hat Israel, Ltd.

发明人： Michael Tsirkin ,  Henri Han van Riel

IPC分类号： G06F13/34

CPC分类号： G06F13/34 ,  G06F9/4812 ,  G06F9/5027 ,  G06F9/5077 ,  G06F2213/2424

摘要： Systems and methods for directly updating the virtual machine memory by interrupt handlers. An example method may comprise: receiving, by a computer system, an interrupt triggered by a physical device; receiving, by an interrupt handling routine, a data frame from the physical device; identifying a virtual machine to receive the interrupt; and responsive to determining that an active memory context on the computer system matches a memory context of the virtual machine, writing, by the interrupt handling routine, the data frame into a memory of the virtual machine.

摘要翻译： 通过中断处理程序直接更新虚拟机内存的系统和方法。 示例性方法可以包括：由计算机系统接收由物理设备触发的中断; 通过中断处理例程从物理设备接收数据帧; 识别虚拟机以接收中断; 并且响应于确定所述计算机系统上的活动存储器上下文与所述虚拟机的存储器上下文匹配，通过所述中断处理例程将所述数据帧写入所述虚拟机的存储器。

公开(公告)号：US09003081B2

公开(公告)日：2015-04-07

申请号：US13512833

申请日：2012-05-18

申请人： Shintaro Kudo ,  Yusuke Nonaka

发明人： Shintaro Kudo ,  Yusuke Nonaka

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F3/06

CPC分类号： G06F13/34 ,  G06F3/0611 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/1642

摘要： The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.

摘要翻译： 本发明是一种集群存储系统，即使当从一个控制器的处理器发送对另一控制器的处理器的访问时，第二控制器的处理器能够对该访问的处理进行优先级处理，以便I / O处理是 也阻止了延迟。 利用本发明的存储系统，第一控制器的第一处理器通过区分由第二控制器的第二处理器处理的请求信息来区分待优先处理的请求信息， 第二处理器和处理不优先的请求信息，并且第二处理器通过区分要优先处理的请求信息和不优先处理的请求信息来获取请求信息。

公开(公告)号：US20140164662A1

公开(公告)日：2014-06-12

申请号：US13710891

申请日：2012-12-11

申请人： OPEN KERNEL LABS, INC.

发明人： Carl Frans van Schaik

IPC分类号： G06F13/26

CPC分类号： G06F13/26 ,  G06F9/4812 ,  G06F9/4818 ,  G06F9/4831 ,  G06F13/24 ,  G06F13/34

摘要： Methods and apparatus for interleaving priorities of a plurality of virtual processors are disclosed. A hypervisor assigns a base priority to each virtual processor and schedules one or more virtual processors to execute on one or more physical processors based on the current priority associated with each virtual processor. When the hypervisor receives an indication from one of the virtual processors that its current priority may be temporarily reduced, the hypervisor lowers the current priority of that virtual processor. The hypervisor then schedules another virtual processor to execute on a physical processor instead of the virtual processor with the temporarily reduced priority. When the hypervisor receives an interrupt for the virtual processor with the lowered priority, the hypervisor raises the priority of that virtual processor and schedules the virtual processor with the restored priority to execute on a physical processor so that processor can handle the interrupt.

摘要翻译： 公开了用于交织多个虚拟处理器的优先级的方法和装置。 虚拟机管理程序为每个虚拟处理器分配基本优先级，并基于与每个虚拟处理器相关联的当前优先级来调度一个或多个虚拟处理器以在一个或多个物理处理器上执行。 当管理程序从虚拟处理器之一接收到其当前优先级可能被暂时减少的指示时，管理程序降低该虚拟处理器的当前优先级。 管理程序然后调度另一个虚拟处理器在物理处理器上执行，而不是虚拟处理器，其优先级暂时降低。 当虚拟机管理程序以优先级较低的虚拟处理器收到中断时，管理程序提高该虚拟处理器的优先级，并以恢复的优先级对虚拟处理器进行调度，以在物理处理器上执行，以便处理器可以处理中断。

公开(公告)号：US20130311685A1

公开(公告)日：2013-11-21

申请号：US13512833

申请日：2012-05-18

申请人： Shintaro Kudo ,  Yusuke Nonaka

发明人： Shintaro Kudo ,  Yusuke Nonaka

IPC分类号： G06F3/00

CPC分类号： G06F13/34 ,  G06F3/0611 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/1642

摘要： The present invention is a clustered storage system with which, even when access to the processor of another controller is sent from the processor of one controller, the processor of the second controller is able to prioritize processing of this access so that I/O processing is also prevented from being delayed. With the storage system of the present invention, the first processor of the first controller transmits request information which is to be processed by the second processor of the second controller to the second processor by differentiating between request information for which processing is to be prioritized by the second processor and request information for which processing is not to be prioritized, and the second processor acquires the request information by differentiating between request information for which processing is to be prioritized and request information for which processing is not to be prioritized.

公开(公告)号：US20090248911A1

公开(公告)日：2009-10-01

申请号：US12057146

申请日：2008-03-27

申请人： DAVID G. CONROY ,  Timothy J. Millet ,  Joseph P. Bratt

发明人： DAVID G. CONROY ,  Timothy J. Millet ,  Joseph P. Bratt

IPC分类号： G06F1/12

CPC分类号： G06F13/34 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3287 ,  G06F13/1673 ,  G06F13/28 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/171

摘要： A method and system is disclosed for accessing I/O and memory devices utilizing a DMA controller. Each device may be connected to the DMA controller through an individual channel. Clocking circuitry in the DMA may allow the DMA controller to send signals to each device at a prescribed frequency. Furthermore, the DMA controller is capable of activating and deactivating a channel clock, used in sending signals to the devices, based on the operational status of the individual devices. The DMA controller is also capable of tuning the channel clock dependant on the capabilities of any active devices. In this manner, the amount of bandwidth used during a DMA data transfer can be tailored to the specific requirements of the devices involved with the data transfer.

摘要翻译： 公开了一种利用DMA控制器访问I / O和存储器件的方法和系统。 每个设备可以通过单独的通道连接到DMA控制器。 DMA中的时钟电路可以允许DMA控制器以规定的频率向每个设备发送信号。 此外，DMA控制器能够基于各个设备的操作状态来激活和去激活用于向设备发送信号的通道时钟。 DMA控制器还能够根据任何有源器件的功能调整通道时钟。 以这种方式，DMA数据传输期间使用的带宽量可以根据与数据传输相关的设备的具体要求进行调整。