公开(公告)号：US20070204098A1

公开(公告)日：2007-08-30

申请号：US11364129

申请日：2006-02-28

申请人： Richard Eguchi ,  Jon Choy

发明人： Richard Eguchi ,  Jon Choy

IPC分类号： G06F12/00

CPC分类号： G06F12/0246

摘要： A non-volatile memory can have multiple blocks erased in parallel for a relatively few number of erase operations. This saves time for the user in the set-up of the memory because the erase operation is relatively slow. Problems with parallel erase relate to different blocks having different program/erase histories with the result that the blocks with different histories erase differently. Thus, after a predetermined number of erase cycles are performed, the ability to parallel erase is prevented. This is achieved by allowing parallel erasing operations until the predetermined number of erase operations have been counted. After that predetermined number has been reached, a parallel erase mode disable signal is generated to prevent further parallel erase cycles. The count and the predetermined number are maintained in a small block of the non-volatile memory that is inaccessible to the user.

摘要翻译： 非易失性存储器可以具有并行擦除多个块，用于相对较少数量的擦除操作。 这样可以节省用户设置存储器的时间，因为擦除操作相对较慢。 并行擦除的问题涉及具有不同程序/擦除历史的不同块，结果是具有不同历史的块被擦除不同。 因此，在执行预定数量的擦除周期之后，防止并行擦除的能力。 这通过允许并行擦除操作直到预定数量的擦除操作被计数来实现。 在达到预定数量之后，产生并行擦除模式禁止信号，以防止进一步的并行擦除周期。 计数和预定数量被保持在用户无法访问的非易失性存储器的小块中。

公开(公告)号：US20060104121A1

公开(公告)日：2006-05-18

申请号：US10991879

申请日：2004-11-18

申请人： Jon Choy ,  Tahmina Akhter

发明人： Jon Choy ,  Tahmina Akhter

IPC分类号： G11C16/04

CPC分类号： G11C16/14

摘要： An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (12), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit (11) controls the discharging of terminals of the memory cell. The discharge rate control circuit (11) includes a reference current generator (34) for providing a reference current. A first current mirror (46) is coupled to the reference current generator (34) and provides a first predetermined discharge current for discharging the control gate, drain, and source. A second current mirror (36) is coupled to the reference current generator (34) and provides a second predetermined discharge current for discharging the well terminals after the erase operation.

摘要翻译： 集成电路包括存储器（10）。 存储器（10）包括非易失性存储器单元的阵列（12）。 阵列（12）的每个存储单元（14）包括多个端子，包括：控制栅极，电荷存储区域，源极，漏极，阱端子和深阱端子。 在阵列（12）的擦除操作之后，擦除电压从每个存储单元放电。 放电速率控制电路（11）控制存储单元的端子的放电。 放电率控制电路（11）包括用于提供参考电流的参考电流发生器（34）。 第一电流镜（46）耦合到参考电流发生器（34），并且提供用于对控制栅极，漏极和源极放电的第一预定放电电流。 第二电流镜（36）耦合到参考电流发生器（34），并提供第二预定放电电流，用于在擦除操作之后对阱端子进行放电。

公开(公告)号：US20060104122A1

公开(公告)日：2006-05-18

申请号：US11120270

申请日：2005-05-02

申请人： Jon Choy

发明人： Jon Choy

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0416 ,  G11C16/14

摘要： An integrated circuit includes a memory (10). The memory (10) includes an array (12) of non-volatile memory cells. Each memory cell (14) of the array (12) includes a plurality of terminals comprising: a control gate, a charge storage region, a source, a drain, a well terminal, and a deep well terminal. Following an erase operation of the array (12), the erase voltages are discharged from each of the memory cells. A discharge rate control circuit (11) controls the discharging of terminals of the memory cell. The discharge rate control circuit (11) includes, for example, a plurality of parallel-connected transistors (112) coupled between the array (12) of non-volatile memory cells and a power supply terminal.

摘要翻译： 集成电路包括存储器（10）。 存储器（10）包括非易失性存储器单元的阵列（12）。 阵列（12）的每个存储单元（14）包括多个端子，包括：控制栅极，电荷存储区域，源极，漏极，阱端子和深阱端子。 在阵列（12）的擦除操作之后，擦除电压从每个存储单元放电。 放电速率控制电路（11）控制存储单元的端子的放电。 放电率控制电路（11）例如包括耦合在非易失性存储单元的阵列（12）和电源端子之间的多个并联的晶体管（112）。

公开(公告)号：US07733126B1

公开(公告)日：2010-06-08

申请号：US12415159

申请日：2009-03-31

申请人： Jon Choy ,  David W. Chrudimsky ,  Padmaraj Sanjeevarao

发明人： Jon Choy ,  David W. Chrudimsky ,  Padmaraj Sanjeevarao

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  G11C16/14 ,  G11C16/30 ,  H03K3/356113

摘要： A first logic state is at a first output voltage level at a first output of a level shifter that selects a first negative regulation voltage level in response to the first logic state. A negative supply voltage begins at first potential and decreases to the first negative regulation voltage level. The first output voltage level decreases as the negative supply voltage decreases. The first output of the level shifter is switched from the first logic state to a second logic state in response to the negative supply voltage reaching the first negative regulation voltage level. The second logic state is provided at a second output voltage level that selects a second negative regulation voltage level for the negative regulation voltage. The first output of the level shifter remains at the second logic state but is reduced in voltage.

摘要翻译： 电平移位器的第一输出处的第一逻辑状态处于第一输出电压电平，其响应于第一逻辑状态选择第一负调节电压电平。 负电源电压从第一个电位开始并降低到第一个负调节电压电平。 第一个输出电压电平随负电源电压降低而减小。 响应于负电源电压达到第一负调节电压电平，电平移位器的第一输出从第一逻辑状态切换到第二逻辑状态。 第二逻辑状态被提供在第二输出电压电平，其选择用于负调节电压的第二负调节电压电平。 电平移位器的第一个输出保持在第二个逻辑状态，但电压降低。

公开(公告)号：US20070222498A1

公开(公告)日：2007-09-27

申请号：US11388396

申请日：2006-03-24

申请人： Jon Choy ,  Tahmina Akhter

发明人： Jon Choy ,  Tahmina Akhter

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： A charge pump system including a clock circuit and a charge pump circuit is provided. The clock circuit provides a first clock with a frequency based on a memory block select signal indicative of load capacitance of a charge node. The charge pump circuit receives the first clock and charges the charge node at a rate based on the frequency of the first clock and the load capacitance of the charge node. The memory block select signal indicates which of the memory blocks are coupled to the charge node and thus indicates the load capacitance of the charge node. The frequency of the first clock is adjusted based on the load capacitance of the selected block so that the slew rate of the charge node is about the same. Thus, the slew rate of the voltage ramp on the charge node is about the same regardless of the load capacitance.

摘要翻译： 提供了包括时钟电路和电荷泵电路的电荷泵系统。 时钟电路提供基于表示充电节点的负载电容的存储块选择信号的频率的第一时钟。 电荷泵电路接收第一时钟并以基于第一时钟的频率和充电节点的负载电容的速率对充电节点充电。 存储器块选择信号指示哪个存储器块耦合到充电节点，并且因此指示充电节点的负载电容。 基于所选块的负载电容来调整第一时钟的频率，使得充电节点的转换速率大致相同。 因此，无论负载电容如何，充电节点上的电压斜坡的转换速率大致相同。

公开(公告)号：US20070279990A1

公开(公告)日：2007-12-06

申请号：US11420558

申请日：2006-05-26

申请人： Jon Choy

发明人： Jon Choy

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C16/06 ,  G11C7/02 ,  G11C11/34

CPC分类号： G11C7/065 ,  G11C7/12 ,  G11C16/26 ,  G11C16/28 ,  G11C2207/2227

摘要： A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a second precharge circuit. The first precharge circuit is for precharging a selected bitline to a first predetermined voltage in response to a first precharge signal. The current-to-voltage converter has a current input coupled to the selected bitline, and a voltage output. A latch circuit has a storage node coupled to the voltage output of the current-to-voltage converter. The second precharge circuit is for precharging the storage node of the latch circuit to a second predetermined voltage in response to a second precharge signal.

摘要翻译： 存储器包括用于感测选定位线的逻辑状态的读出放大器。 读出放大器包括第一预充电电路，电流 - 电压转换器，锁存电路和第二预充电电路。 第一预充电电路用于响应于第一预充电信号将选定位线预充电到第一预定电压。 电流 - 电压转换器具有耦合到所选位线的电流输入和电压输出。 锁存电路具有耦合到电流 - 电压转换器的电压输出的存储节点。 第二预充电电路用于响应于第二预充电信号将锁存电路的存储节点预充电到第二预定电压。