公开(公告)号：US20180299962A1

公开(公告)日：2018-10-18

申请号：US15566495

申请日：2016-04-14

申请人： Richard FOSS ,  DSP4YOU Ltd.

发明人： Richard FOSS ,  Antoine ROUGET

IPC分类号： G06F3/01 ,  H04S7/00 ,  H04R5/02

CPC分类号： G06F3/017 ,  H04R5/02 ,  H04S7/30 ,  H04S7/303 ,  H04S2400/11

摘要： Systems and methods for positioning an output element (102, 602) within a three-dimensional environment (104, 604) are described. Movement data relating to movement of a mobile device (120, 620) is obtained (206, 262). The movement data is mapped (208, 264) to movement of a simulated output element (503) in a virtual environment (505), which simulates the three-dimensional environment. The movement of the simulated output element is associated with movement of an output element within the three-dimensional environment so as to control the position of the output element within the three-dimensional environment. In one exemplary embodiment an output element (102) being a sound source is positioned in a three-dimensional, immersive sound environment (104). In another exemplary embodiment a focal point of a light beam (602) is positioned in a three-dimensional theatrical environment (604). The described systems and methods enable a user to control the real-time and/or recorded position and/or movement of an output element by manipulating the orientation of a mobile device (120, 620).

公开(公告)号：US20070300100A1

公开(公告)日：2007-12-27

申请号：US11830077

申请日：2007-07-30

申请人： Richard FOSS

发明人： Richard FOSS

IPC分类号： G06F11/00

CPC分类号： H03M13/29 ,  G06F11/1044 ,  H03M13/095

摘要： An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storing row parity bits, and the parity block stores column parity bits. A row parity circuit coupled in parallel to an existing local databus of each memory checks the parity of the local databus bits against a row parity bit during a refresh or read operation to identify parity failure. Identification of the incorrect bit of the word is achieved by iteratively transferring the data of the local databus of each memory block onto an existing global databus, and checking the parity across the global databus with a column parity circuit. When global databus parity failure is detected, all bits of the global databus are inverted to purge the incorrect bit from the memory block via the local databus.

摘要翻译： 用于清除数据错误的嵌入式DRAM ECC架构。 嵌入式DRAM ECC架构基于二维线性奇偶校验方案，并且包括多个存储块和奇偶校验块。 每个存储块包括用于存储行奇偶校验位的附加列，并且奇偶校验块存储列奇偶校验位。 与每个存储器的现有局部数据总线并联耦合的行奇偶校验电路在刷新或读取操作期间检查本地数据总线位与奇偶校验位的奇偶校验，以识别奇偶校验故障。 通过将每个存储器块的本地数据总线的数据迭代地传送到现有的全局数据总线上，并通过列奇偶校验电路检查全局数据总线上的奇偶校验来实现字的不正确位的识别。 当检测到全局数据总线奇偶校验故障时，全局数据总线的所有位都被反相，以通过本地数据总线从存储块中清除错误的位。