公开(公告)号：US07696540B2

公开(公告)日：2010-04-13

申请号：US11644578

申请日：2006-12-22

申请人： Richard Francis ,  Yang Yu Fan ,  Eric Johnson ,  Hy Hoang

发明人： Richard Francis ,  Yang Yu Fan ,  Eric Johnson ,  Hy Hoang

IPC分类号： H01L29/80

CPC分类号： H01L29/872 ,  H01L27/0641 ,  H01L27/0814 ,  H01L27/0817 ,  H01L29/0623 ,  H01L29/7722 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/8725

摘要： An apparatus and method for a fast recovery rectifier structure. Specifically, the structure includes a substrate of a first dopant. A first epitaxial layer lightly doped with the first dopant is coupled to the substrate. A first metallization layer is coupled to the first epitaxial layer. A plurality of trenches is recessed into the first epitaxial layer, each of which is coupled to the metallization layer. The device also includes a plurality of wells each doped with a second dopant type, wherein each well is formed beneath and adjacent to a corresponding trench. A plurality of oxide layers is formed on walls and a bottom of a corresponding trench. A plurality of channel regions doped with the first dopant is formed within the first epitaxial layer between two corresponding wells. Each of the plurality of channel regions is more highly doped with the first dopant than the first epitaxial layer.

摘要翻译： 一种快速恢复整流器结构的装置和方法。 具体地，该结构包括第一掺杂剂的衬底。 轻掺杂有第一掺杂剂的第一外延层耦合到衬底。 第一金属化层耦合到第一外延层。 多个沟槽凹陷到第一外延层中，每个沟槽耦合到金属化层。 该器件还包括多个孔，每个阱均掺杂有第二掺杂剂类型，其中每个阱形成在相应沟槽的下面并与其相邻。 多个氧化物层形成在相应沟槽的壁和底部上。 掺杂有第一掺杂剂的多个沟道区在两个对应的阱之间的第一外延层内形成。 多个沟道区中的每一个与第一外延层比第一掺杂物更加高掺杂。

公开(公告)号：US20070145429A1

公开(公告)日：2007-06-28

申请号：US11644578

申请日：2006-12-22

申请人： Richard Francis ,  Yang Fan ,  Eric Johnson ,  Hy Hoang

发明人： Richard Francis ,  Yang Fan ,  Eric Johnson ,  Hy Hoang

IPC分类号： H01L29/80

CPC分类号： H01L29/872 ,  H01L27/0641 ,  H01L27/0814 ,  H01L27/0817 ,  H01L29/0623 ,  H01L29/7722 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/8725

摘要： An apparatus and method for a fast recovery rectifier structure. Specifically, the structure includes a substrate of a first dopant. A first epitaxial layer lightly doped with the first dopant is coupled to the substrate. A first metallization layer is coupled to the first epitaxial layer. A plurality of trenches is recessed into the first epitaxial layer, each of which is coupled to the metallization layer. The device also includes a plurality of wells each doped with a second dopant type, wherein each well is formed beneath and adjacent to a corresponding trench. A plurality of oxide layers is formed on walls and a bottom of a corresponding trench. A plurality of channel regions doped with the first dopant is formed within the first epitaxial layer between two corresponding wells. Each of the plurality of channel regions is more highly doped with the first dopant than the first epitaxial layer.

摘要翻译： 一种快速恢复整流器结构的装置和方法。 具体地，该结构包括第一掺杂剂的衬底。 轻掺杂有第一掺杂剂的第一外延层耦合到衬底。 第一金属化层耦合到第一外延层。 多个沟槽凹陷到第一外延层中，每个沟槽耦合到金属化层。 该器件还包括多个孔，每个阱均掺杂有第二掺杂剂类型，其中每个阱形成在相应沟槽的下面并与其相邻。 多个氧化物层形成在相应沟槽的壁和底部上。 掺杂有第一掺杂剂的多个沟道区在两个对应的阱之间的第一外延层内形成。 多个沟道区中的每一个与第一外延层比第一掺杂物更加高掺杂。

公开(公告)号：US06233721B1

公开(公告)日：2001-05-15

申请号：US09270738

申请日：1999-03-16

申请人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F1500

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

摘要翻译： 一种在芯片上制造电力总线的方法，其中电源总线上产生狭缝。 本发明涉及一种制造电源总线的方法，其中对布线数据库的参考表示芯片中电源总线的坐标位置。 电源总线的高度和宽度根据其坐标进行计算。 基于电源总线的高度和宽度以及功率狭缝之间的预定尺寸和间隔，确定要产生的多个功率狭缝。 然后通过在布局数据库的坐标中将功率狭缝添加到电源总线来产生这些功率狭缝。 本发明的方法还产生用于在电源总线重叠的情况下制造芯片上的电源总线的电源插槽。

公开(公告)号：US06378120B2

公开(公告)日：2002-04-23

申请号：US09758367

申请日：2001-01-12

申请人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F1750

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

摘要翻译： 一种在芯片上制造电力总线的方法，其中电源总线上产生狭缝。 本发明涉及一种制造电源总线的方法，其中参考布局数据库显示芯片中电源总线的坐标位置。 电源总线的高度和宽度根据其坐标进行计算。 基于电源总线的高度和宽度以及功率狭缝之间的预定尺寸和间隔，确定要产生的多个功率狭缝。 然后通过在布局数据库的坐标中将功率狭缝添加到电源总线来产生这些功率狭缝。 本发明的方法还产生用于在电源总线重叠的情况下制造芯片上的电源总线的电源插槽。

公开(公告)号：US5726904A

公开(公告)日：1998-03-10

申请号：US665846

申请日：1996-06-19

申请人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F17/50 ,  H01L23/528 ,  G06F15/00

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002

摘要： An automatic method of generating slits in power buses on a chip. The present invention includes three embodiments. The first embodiment is directed to a generic method of generating power slits. Once bus dimensions are identified, predetermined parameters for optimal power slit size and number are used to automatically generate a power slit layer for the mask database. The second embodiment is a continuation of the first embodiment and is directed to a method of generating power slits for an orthogonal corner case; where two buses overlap at 90.degree. angles. This is performed by locating all corner cases. Power slits are removed within a cross (corner/intersect) area of overlapping buses. At this point power slits from overlapping buses are extended across the corner/intersect area. The extension lines are logically ANDed together/resulting in points within the corner/intersect area where the extension lines intersect. These intersection points indicate where new types of power slits, called "holes", can be generated. The third embodiment is directed to a method of generating power slits for non-orthogonal corner case. It is generally identical to the second embodiment.

摘要翻译： 一种在芯片上的电源总线上产生狭缝的自动方法。 本发明包括三个实施例。 第一实施例涉及产生动力狭缝的通用方法。 一旦确定了总线尺寸，则使用用于最佳功率狭缝尺寸和数量的预定参数来自动生成掩模数据库的功率狭缝层。 第二实施例是第一实施例的延续，并且涉及一种用于产生正交拐角箱的动力狭缝的方法; 其中两条公共汽车在90度角重叠。 这是通过定位所有角箱来执行的。 在重叠总线的交叉（拐角/相交）区域内移除动力狭缝。 在这一点上，来自重叠总线的动力狭缝在拐角/交叉区域延伸。 延伸线在逻辑上与之并联，导致延伸线相交的拐角/交叉区域内的点。 这些交点表示可以生成称为“孔”的新型电源狭缝的位置。 第三实施例涉及一种用于产生用于非正交角箱的功率狭缝的方法。 它通常与第二实施例相同。

公开(公告)号：US07516436B2

公开(公告)日：2009-04-07

申请号：US11483638

申请日：2006-07-11

申请人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F17/50

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

摘要翻译： 一种在芯片上制造电力总线的方法，其中电源总线上产生狭缝。 本发明涉及一种制造电源总线的方法，其中参考布局数据库显示芯片中电源总线的坐标位置。 电源总线的高度和宽度根据其坐标进行计算。 基于电源总线的高度和宽度以及功率狭缝之间的预定尺寸和间隔，确定要产生的多个功率狭缝。 然后通过在布局数据库的坐标中将功率狭缝添加到电源总线来产生这些功率狭缝。 本发明的方法还产生用于在电源总线重叠的情况下制造芯片上的电源总线的电源插槽。

公开(公告)号：US20050086625A1

公开(公告)日：2005-04-21

申请号：US10973896

申请日：2004-10-27

申请人： Chong Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F17/50 ,  H01L23/528

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

摘要翻译： 一种在芯片上制造电力总线的方法，其中电源总线上产生狭缝。 本发明涉及一种制造电源总线的方法，其中对布线数据库的参考表示芯片中电源总线的坐标位置。 电源总线的高度和宽度根据其坐标进行计算。 基于电源总线的高度和宽度以及功率狭缝之间的预定尺寸和间隔，确定要产生的多个功率狭缝。 然后通过在布局数据库的坐标中将功率狭缝添加到电源总线来产生这些功率狭缝。 本发明的方法还产生用于在电源总线重叠的情况下制造芯片上的电源总线的电源插槽。

公开(公告)号：US06842885B2

公开(公告)日：2005-01-11

申请号：US10077940

申请日：2002-02-20

申请人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong Ming Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F17/50 ,  H01L23/528

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

摘要翻译： 一种在芯片上制造电力总线的方法，其中电源总线上产生狭缝。 本发明涉及一种制造电源总线的方法，其中参考布局数据库显示芯片中电源总线的坐标位置。 电源总线的高度和宽度根据其坐标进行计算。 基于电源总线的高度和宽度以及功率狭缝之间的预定尺寸和间隔，确定要产生的多个功率狭缝。 然后通过在布局数据库的坐标中将功率狭缝添加到电源总线来产生这些功率狭缝。 本发明的方法还产生用于在电源总线重叠的情况下制造芯片上的电源总线的电源插槽。

公开(公告)号：US5561789A

公开(公告)日：1996-10-01

申请号：US455133

申请日：1995-05-31

申请人： Chong M. Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong M. Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F17/50 ,  H01L23/528 ,  G06F1/18 ,  G06F13/00

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002

摘要： An intersect area of an apparatus having a plurality of power buses, and a method for making the same. An intersect area is defined by an overlap region where a first and second power bus overlap. The power buses can overlap at orthogonal and non-orthogonal angles. Each power bus has a vertical and horizontal axis, along which power flows. Power slits are located along two axes. The intersect area of the apparatus is void of power slits, but has holes at intersection points of a set of pointer lines. The pointer lines are imaginary lines emanating from the power slits.

摘要翻译： 具有多个电力母线的装置的交叉区域及其制造方法。 交叉区域由第一和第二电力总线重叠的重叠区域限定。 电力总线可以在正交和非正交角度重叠。 每个电源总线都有一个垂直和水平的轴，电源沿着它们流动。 电源狭缝位于两个轴上。 设备的交叉区域没有功率狭缝，但是在一组指针线的交点处具有孔。 指针线是从功率狭缝发出的假想线。

公开(公告)号：US5461578A

公开(公告)日：1995-10-24

申请号：US289278

申请日：1994-08-11

申请人： Chong M. Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

发明人： Chong M. Lin ,  Tatao Chuang ,  Tran Long ,  Hy Hoang

IPC分类号： G06F17/50 ,  H01L23/528

CPC分类号： H01L23/5286 ,  G06F17/5068 ,  H01L2924/0002

摘要： A power bus having power slits embodied therein. The present invention includes three embodiments. The first embodiment is directed to generic power buses. Each power bus has a first axis, along which power flows, and a second axis. Each of the power slits have an identical maximum width and minimum length. Power slits located along the first axis are separated from one another by a first minimum value, and power slits located along the second axis are separated from one another by a second minimum value. The first and second minimum values are selected as a function of electron flow and photolithography. The second embodiment is a continuation of the first embodiment and is directed to an apparatus with a plurality of power buses in which two buses overlap at 90.degree. angles. The overlap area of the apparatus is void of power slits, but has holes at intersection points of a set of pointer lines. The pointer lines are imaginary lines eminating from the power slits. The third embodiment is directed to an apparatus with a plurality of power buses in which two power buses overlap at a non-orthogonal angle. The overlap area in this third embodiment is generally identical to that of the second embodiment.

摘要翻译： 具有体现在其中的动力狭缝的电力总线。 本发明包括三个实施例。 第一实施例涉及通用电力总线。 每个电力总线具有第一轴，功率沿其流动，第二轴具有第一轴。 每个功率狭缝具有相同的最大宽度和最小长度。 沿着第一轴线定位的动力狭缝彼此分开第一最小值，并且沿着第二轴线定位的动力狭缝彼此分开第二最小值。 选择第一和第二最小值作为电子流和光刻的函数。 第二实施例是第一实施例的延续，并且涉及具有多个电力总线的装置，其中两个总线以90°角重叠。 该装置的重叠区域没有功率狭缝，但是在一组指针线的交点处具有孔。 指针线是从功率狭缝排出的假想线。 第三实施例涉及具有多个电源总线的装置，其中两个电源总线以非正交角度重叠。 该第三实施例中的重叠区域与第二实施例大致相同。