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1.发明授权公开(公告)号：US08635381B2
公开(公告)日：2014-01-21
申请号：US12869591
申请日：2010-08-26
IPC分类号： G06F3/00
CPC分类号： G06F11/3485 , G06F2201/88
摘要： According to one aspect of the present disclosure a method and technique for monitoring memory access is disclosed. The method includes monitoring, by a plurality of memory controllers, access to a memory unit, wherein each memory controller is associated with a different range of memory addresses of the memory unit, and wherein each memory controller monitors access for its associated range of memory addresses. The method also includes updating an incrementor with access data corresponding to accesses to the memory unit, wherein each memory controller updates the access data based on access of its associated range of memory addresses. The method further includes storing, by each respective memory controller, the updated access data in a cache corresponding to the respective range of memory addresses and, responsive to the updated access data for a respective range of memory addresses exceeding a threshold, storing the access data for the respective range of memory addresses in memory unit.
摘要翻译： 根据本公开的一个方面，公开了一种用于监视存储器访问的方法和技术。 该方法包括通过多个存储器控制器监视对存储器单元的访问，其中每个存储器控制器与存储器单元的存储器地址的不同范围相关联，并且其中每个存储器控制器监视对其相关联的存储器地址范围的访问 。 该方法还包括使用与对存储器单元的访问相对应的访问数据来更新增量器，其中每个存储器控制器基于其相关联的存储器地址范围的访问来更新访问数据。 该方法还包括由每个相应的存储器控制器将更新的访问数据存储在与存储器地址的相应范围相对应的高速缓存中，并且响应于对于超过阈值的存储器地址的相应范围的更新的访问数据，存储访问数据 对于存储器单元中的各个存储器地址范围。
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2.发明申请公开(公告)号：US20120054375A1
公开(公告)日：2012-03-01
申请号：US12869591
申请日：2010-08-26
CPC分类号： G06F11/3485 , G06F2201/88
摘要： According to one aspect of the present disclosure a method and technique for monitoring memory access is disclosed. The method includes monitoring, by a plurality of memory controllers, access to a memory unit, wherein each memory controller is associated with a different range of memory addresses of the memory unit, and wherein each memory controller monitors access for its associated range of memory addresses. The method also includes updating an incrementor with access data corresponding to accesses to the memory unit, wherein each memory controller updates the access data based on access of its associated range of memory addresses. The method further includes storing, by each respective memory controller, the updated access data in a cache corresponding to the respective range of memory addresses and, responsive to the updated access data for a respective range of memory addresses exceeding a threshold, storing the access data for the respective range of memory addresses in memory unit.
摘要翻译： 根据本公开的一个方面，公开了一种用于监视存储器访问的方法和技术。 该方法包括通过多个存储器控制器监视对存储器单元的访问，其中每个存储器控制器与存储器单元的存储器地址的不同范围相关联，并且其中每个存储器控制器监视对其相关联的存储器地址范围的访问 。 该方法还包括使用与对存储器单元的访问相对应的访问数据来更新增量器，其中每个存储器控制器基于其相关联的存储器地址范围的访问来更新访问数据。 该方法还包括由每个相应的存储器控制器将更新的访问数据存储在与存储器地址的相应范围相对应的高速缓存中，并且响应于对于超过阈值的存储器地址的相应范围的更新的访问数据，存储访问数据 对于存储器单元中的各个存储器地址范围。
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公开(公告)号：US08645640B2
公开(公告)日：2014-02-04
申请号：US13166054
申请日：2011-06-22
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
摘要翻译： 公开了一种用于在具有多个小灯的数据处理系统内提供系统存储器使用限制的装置。 该装置包括系统存储器，存储器访问收集模块，存储器信用计费模块和存储器调节计数器。 存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。 存储器信用计费模块根据从小巧的第一和第二高速缓存存储器的第一和第二组信号中提取的高速缓存访问的结果来跟踪每用户虚拟分区上的系统存储器的使用情况。 存储器油门计数器用于提供节气门控制信号，以防止当系统存储器使用量超过预定值时对系统存储器的访问。
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4.发明授权公开(公告)号：US08930589B2
公开(公告)日：2015-01-06
申请号：US12869535
申请日：2010-08-26
CPC分类号： G06F11/3442 , G06F11/3476 , G06F2201/88 , G06F2201/885
摘要： According to one aspect of the present disclosure a method and technique for monitoring memory access is disclosed. The method includes monitoring access to a memory unit, updating an activity cache associated with an incrementor with access data corresponding to accesses to the memory unit, monitoring a rate of access to the memory unit, adjusting a sample rate of the access data for storage in the memory unit based on the rate of access, and scaling a value of the access data based on the sample rate.
摘要翻译： 根据本公开的一个方面，公开了一种用于监视存储器访问的方法和技术。 该方法包括监视对存储器单元的访问，使用与对存储器单元的访问相对应的访问数据来更新与增量器相关联的活动高速缓存，监视对存储器单元的访问速率，调整访问数据的采样率以便存储 基于访问速率的存储器单元，以及基于采样率来缩放访问数据的值。
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公开(公告)号：US20130151578A1
公开(公告)日：2013-06-13
申请号：US13598847
申请日：2012-08-30
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
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6.发明申请公开(公告)号：US20120054374A1
公开(公告)日：2012-03-01
申请号：US12869535
申请日：2010-08-26
IPC分类号： G06F3/00
CPC分类号： G06F11/3442 , G06F11/3476 , G06F2201/88 , G06F2201/885
摘要： According to one aspect of the present disclosure a method and technique for monitoring memory access is disclosed. The method includes monitoring access to a memory unit, updating an activity cache associated with an incrementor with access data corresponding to accesses to the memory unit, monitoring a rate of access to the memory unit, adjusting a sample rate of the access data for storage in the memory unit based on the rate of access, and scaling a value of the access data based on the sample rate.
摘要翻译： 根据本公开的一个方面，公开了一种用于监视存储器访问的方法和技术。 该方法包括监视对存储器单元的访问，使用与对存储器单元的访问相对应的访问数据来更新与增量器相关联的活动高速缓存，监视对存储器单元的访问速率，调整访问数据的采样率以便存储 基于访问速率的存储器单元，以及基于采样率来缩放访问数据的值。
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7.发明授权公开(公告)号：US08984041B2
公开(公告)日：2015-03-17
申请号：US13598847
申请日：2012-08-30
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
摘要翻译： 提供了用于在数据处理系统中执行浮点算术运算的机构。 接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。 存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值， 至少一个浮点操作数的尾数的位的范围。 基于向量值和多个浮点操作数，生成用于浮点运算的结果值。
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8.发明授权公开(公告)号：US08909690B2
公开(公告)日：2014-12-09
申请号：US13324025
申请日：2011-12-13
IPC分类号： G06F7/38
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
摘要翻译： 提供了用于在数据处理系统中执行浮点算术运算的机构。 接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。 存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值， 至少一个浮点操作数的尾数的位的范围。 基于向量值和多个浮点操作数，生成用于浮点运算的结果值。
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公开(公告)号：US08683160B2
公开(公告)日：2014-03-25
申请号：US13165982
申请日：2011-06-22
IPC分类号： G06F12/00
CPC分类号： G06Q50/10 , G06F12/0897
摘要： An apparatus for providing memory energy accounting within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory throttle counter, and a memory credit accounting module. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet.
摘要翻译： 公开了一种用于在具有多个小灯的数据处理系统内提供存储器能量记帐的装置。 该装置包括系统存储器，存储器访问收集模块，存储器调节计数器和存储器信用计费模块。 存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。 存储器信用计费模块根据从小巧的第一和第二高速缓冲存储器的第一和第二组信号提取的高速缓存访问的结果跟踪每个用户的系统存储器的使用情况。
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公开(公告)号：US08650367B2
公开(公告)日：2014-02-11
申请号：US13585268
申请日：2012-08-14
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory A. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory A. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
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