摘要:
A fast centralized arbitrator for avoiding contention between up to eight processors or other smart devices having access to a shared computer facility. Each of the processors or smart devices is assigned a unique three digit octal formatted priority level. A first set of 1-of-8 decoders, AND gates and a prioritizer circuit are employed to determine the priority level of the highest priority device requesting access to the shared facility. A second set of 1-of-8 decoders, each having associated therewith a set of OR gates for combining the decoder outputs with the outputs of the prioritizer circuit and an AND gate for combining the outputs of the set of OR gates, are employed to generate a set of acknowledge signals for the smart devices.
摘要:
A programmable logic device (PLD) comprising a configuration controller. The configuration controller may be configured to (i) retrieve data and (ii) program a number of configuration bits of the PLD in response to the data.
摘要:
An apparatus comprising a first circuit comprising a JTAG port and a second port. A JTAG non-compliant circuit may be controlled by the JTAG port when connected to the second port.