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公开(公告)号：US4564941A
公开(公告)日：1986-01-14
申请号：US559210
申请日：1983-12-08
CPC分类号： H03M13/09 , G11B20/1866 , H03M13/27
摘要： The present invention provides methods and apparatus for improved error detection in a data processing system. The techniques of the present invention insure that there is a high probability that an error in a record of data (each record comprising a plurality of data bits) is detected. In the event of an error, the present invention applies a randomizing function to the error which modifies subsequent bits within the record and then propagates and further randomizes the error throughout the record to magnify its apparent size. The randomizing and propagation of the error significantly lowers the misdetection probability for random errors within a record, in that error detectability is no longer pattern sensitive. The use of both propagation and randomization functions significantly alters the data containing an error, such that a high probability of detection using check-sum techniques exists.
摘要翻译： 本发明提供了一种用于在数据处理系统中改进错误检测的方法和装置。 本发明的技术确保了检测到数据记录（包括多个数据位的每个记录）的错误的可能性很高。 在发生错误的情况下，本发明将随机化函数应用于修改记录中的后续位的误差，然后传播并进一步随机化整个记录中的误差以放大其表观尺寸。 错误的随机化和传播显着降低了记录内随机误差的错误检测概率，因为错误检测能力不再是模式敏感的。 传播和随机化功能的使用显着地改变了包含错误的数据，使得存在使用校验和技术的高概率检测技术。
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2.发明授权公开(公告)号：US07925912B1
公开(公告)日：2011-04-12
申请号：US11831554
申请日：2007-07-31
IPC分类号： G06F1/00 , G06F1/12 , G06F19/00 , G06F15/167 , G06F3/00 , G06F12/00 , H03K19/00 , H03K5/01 , H03K21/00 , H04L7/00
摘要： A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.
摘要翻译： 公开了一种用于调整响应于参考脉冲而产生的输出脉冲的至少一个边沿的定时的装置。 这样的设备可以包括具有两个或更多个第一存储器单元的第一存储器电路和还具有两个或更多个第二存储器单元的第二存储器电路。 第一存储器电路可以被配置为在第一采样时钟的上升沿周期性地对参考脉冲进行采样，而第二存储器电路可以被配置为在第一采样时钟的下降沿周期性地对参考脉冲进行采样。 还可以包括组合逻辑电路以基于由第一和/或第二存储器电路提供的一组定时指令和定时信息来产生具有至少一个调整边缘的输出脉冲。
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3.发明授权公开(公告)号：US08549342B1
公开(公告)日：2013-10-01
申请号：US13080079
申请日：2011-04-05
摘要： A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.
摘要翻译： 公开了一种用于调整响应于参考脉冲而产生的输出脉冲的至少一个边沿的定时的装置。 这样的设备可以包括具有两个或更多个第一存储器单元的第一存储器电路和还具有两个或更多个第二存储器单元的第二存储器电路。 第一存储器电路可以被配置为在第一采样时钟的上升沿周期性地对参考脉冲进行采样，而第二存储器电路可以被配置为在第一采样时钟的下降沿周期性地对参考脉冲进行采样。 还可以包括组合逻辑电路以基于由第一和/或第二存储器电路提供的一组定时指令和定时信息来产生具有至少一个调整边缘的输出脉冲。
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