公开(公告)号：US4564941A

公开(公告)日：1986-01-14

申请号：US559210

申请日：1983-12-08

申请人： Richard N. Woolley ,  Neal Glover ,  Richard Williams

发明人： Richard N. Woolley ,  Neal Glover ,  Richard Williams

IPC分类号： G06F11/10 ,  G06F11/00 ,  G11B20/18 ,  H03M13/09 ,  H03M13/27

CPC分类号： H03M13/09 ,  G11B20/1866 ,  H03M13/27

摘要： The present invention provides methods and apparatus for improved error detection in a data processing system. The techniques of the present invention insure that there is a high probability that an error in a record of data (each record comprising a plurality of data bits) is detected. In the event of an error, the present invention applies a randomizing function to the error which modifies subsequent bits within the record and then propagates and further randomizes the error throughout the record to magnify its apparent size. The randomizing and propagation of the error significantly lowers the misdetection probability for random errors within a record, in that error detectability is no longer pattern sensitive. The use of both propagation and randomization functions significantly alters the data containing an error, such that a high probability of detection using check-sum techniques exists.

摘要翻译： 本发明提供了一种用于在数据处理系统中改进错误检测的方法和装置。 本发明的技术确保了检测到数据记录（包括多个数据位的每个记录）的错误的可能性很高。 在发生错误的情况下，本发明将随机化函数应用于修改记录中的后续位的误差，然后传播并进一步随机化整个记录中的误差以放大其表观尺寸。 错误的随机化和传播显着降低了记录内随机误差的错误检测概率，因为错误检测能力不再是模式敏感的。 传播和随机化功能的使用显着地改变了包含错误的数据，使得存在使用校验和技术的高概率检测技术。

公开(公告)号：US07957370B2

公开(公告)日：2011-06-07

申请号：US12126188

申请日：2008-05-23

申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

IPC分类号： H04L12/50

CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1258 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B2020/1476 ,  H03M13/31

摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

摘要翻译： 公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道 。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。 这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。 公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。

公开(公告)号：US5909331A

公开(公告)日：1999-06-01

申请号：US823393

申请日：1997-03-19

申请人： Richard T. Behrens ,  Trent O. Dudley ,  Neal Glover

发明人： Richard T. Behrens ,  Trent O. Dudley ,  Neal Glover

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31

CPC分类号： G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. The read channel further employs an error tolerant sync mark detector, as well as a sync mark recovery procedure for synchronizing to the data when the sync mark is destroyed by a defect.

摘要翻译： 公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列 使用离散时间序列检测器从滤波后的样本值。 读通道还采用容错同步标记检测器，以及当同步标记被缺陷破坏时同步到数据的同步标记恢复过程。

公开(公告)号：US5844509A

公开(公告)日：1998-12-01

申请号：US820926

申请日：1997-03-19

申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/14 ,  G11B20/18 ,  G11B27/30 ,  H03M13/31 ,  H03M7/46

CPC分类号： G11B20/10055 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B5/012 ,  G11B5/09 ,  H03M13/31 ,  G11B20/1258 ,  G11B2020/1476

摘要： A synchronous read channel is disclosed which samples an analog read signal from a magnetic read head positioned over a magnetic disk medium, filters the sample values according to a desired partial response, extracts timing information from the filtered sample values, and detects an estimated data sequence from the filtered sample values using a discrete time sequence detector. The read channel employs a Data Randomizer which processes unencoded user data to insure that the channel bit patterns with worst-case pattern sensitivity occur no more frequently than would be expected from random user data. The Data Randomizer employs two linear feedback shift registers: one generates a 63-bit sequence which is EXLUSIVE-OR-ed against the MSB of each pair of data bits, the other generates a 127-bit sequence which is EXCLUSIVE-OR-ed against the LSB of each pair of data bits. The Data Randomizer does not affect error propagation. When the Data Randomizer is enabled, the probability of encountering any specific pattern of length n channel bits at a randomly selected location within encoded data is approximately 1/2.sup.n.

摘要翻译： 公开了一种同步读通道，其从位于磁盘介质上的磁读头读取模拟读信号，根据所需的部分响应对采样值进行滤波，从滤波后的采样值中提取定时信息，并检测估计数据序列 使用离散时间序列检测器从滤波后的样本值。 读通道采用数据随机化器，其处理未编码的用户数据，以确保具有最坏情况模式灵敏度的信道位模式不会比从随机用户数据预期的更频繁地发生。 数据随机化器采用两个线性反馈移位寄存器：一个产生一个63位的序列，它与每对数据位的MSB相对而言是EXLUSIVE-OR-，另一个产生一个127位的序列，它是独占 每对数据位的LSB。 Data Randomizer不影响错误传播。 当启用数据随机器时，在编码数据内随机选择的位置遇到长度为n个通道位的任何特定模式的概率大约为+ E，fra 1/2 + EE n。

公开(公告)号：US5751733A

公开(公告)日：1998-05-12

申请号：US710293

申请日：1996-09-16

申请人： Neal Glover

发明人： Neal Glover

IPC分类号： G11B20/18

CPC分类号： G11B20/1866

摘要： A disc drive storage system is disclosed that employs sector level and track level error correction systems (ECS), wherein the track level error correction capability is increased by interleaving the track level redundancy. In the preferred embodiment, each sector on the disc is divided into three interleaves or codewords with sector level redundancy generated for each interleaved codeword. The track level redundancy is then generated by combining the interleaved codewords separately according to a predetermined error correction operation (e.g., byte XOR) to form an interleaved redundancy sector. During readback, the sector level ECS generates an erasure pointer corresponding to an uncorrectable codeword within a sector for use by the track level ECS. In this manner, the track level ECS can correct up to three uncorrectable sectors when three sectors contain a single uncorrectable codeword in separate interleaves.

摘要翻译： 公开了一种采用扇区级和磁道级纠错系统（ECS）的磁盘驱动器存储系统，其中通过交织磁道级冗余来提高磁道级纠错能力。 在优选实施例中，盘上的每个扇区被划分成为每个交织的码字产生扇区级冗余的三个交织或码字。 然后通过根据预定的纠错操作（例如，字节XOR）单独组合交织的码字来产生轨道级冗余，以形成交织的冗余扇区。 在回读期间，扇区级ECS生成与扇区内的不可校正码字对应的擦除指针，以由轨道级ECS使用。 以这种方式，当三个扇区在单独的交织中包含单个不可校正的码字时，轨道电平ECS可校正多达三个不可校正扇区。

公开(公告)号：US5473620A

公开(公告)日：1995-12-05

申请号：US124938

申请日：1993-09-21

申请人： Christopher P. Zook ,  Neal Glover

发明人： Christopher P. Zook ,  Neal Glover

IPC分类号： G06F11/10 ,  H03M13/00 ,  H03M13/15

CPC分类号： G06F11/1004 ,  G06F11/10 ,  H03M13/151

摘要： An apparatus and method of generating redundancy symbols and syndromes which is order-programmable is disclosed. The apparatus and method involves the implementation of an error correcting encoder/decoder for polynomial codes which uses a single circuit to generate check symbols during the transmit operation and to generate syndromes during a receive operation. The selection of roots for the code generator, and hence, the code order is programmable.

摘要翻译： 公开了一种生成可编程序列的冗余符号和校正子的装置和方法。 该装置和方法包括实施用于多项式代码的纠错编码器/解码器，其使用单个电路在发送操作期间产生校验符号并且在接收操作期间产生校正符号。 代码生成器的根的选择，因此代码顺序是可编程的。

公开(公告)号：US5297184A

公开(公告)日：1994-03-22

申请号：US12049

申请日：1993-02-01

申请人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

发明人： Richard T. Behrens ,  Trent Dudley ,  Neal Glover

IPC分类号： G11B5/09 ,  G11B20/10 ,  H03G3/20 ,  H04L27/08

CPC分类号： H03G3/001 ,  G11B20/10009 ,  H03G3/3036

摘要： A mixed analog and digital gain control circuit for controlling the amplitude of an analog input signal. The circuit has a variable gain amplifier that receives the signal from a read/write recording head preamplifier. The output of the variable gain amplifier is connected through a multiplexer and equalizer to an analog to digital converter for converting the analog signal to digital sample values at controlled sampling times. A gain control circuit receives the digital values and the output of a pulse detector indicating when a pulse has occurred. A gain error detector within the gain control circuit determines the amount of error in the amplitude of each detected pulse, and this error amount is filtered and sent through a digital to analog converter and then through an exponentiating circuit. The output of the exponentiating circuit is connected to a gain control input of the variable gain amplifier.

摘要翻译： 一种混合的模拟和数字增益控制电路，用于控制模拟输入信号的幅度。 该电路具有可变增益放大器，其接收来自读/写记录头前置放大器的信号。 可变增益放大器的输出通过多路复用器和均衡器连接到模数转换器，用于在受控采样时将模拟信号转换为数字采样值。 增益控制电路接收指示何时发生脉冲的数字值和脉冲检测器的输出。 增益控制电路内的增益误差检测器确定每个检测脉冲幅度的误差量，并将该误差量滤波并通过数模转换器发送，然后通过取幂电路。 指数电路的输出连接到可变增益放大器的增益控制输入。

公开(公告)号：US5280488A

公开(公告)日：1994-01-18

申请号：US612430

申请日：1990-11-08

申请人： Neal Glover ,  Trent Dudley

发明人： Neal Glover ,  Trent Dudley

IPC分类号： G11B20/18 ,  H03M13/15 ,  H03M13/17 ,  G06F11/10

CPC分类号： H03M13/151 ,  G11B20/1833 ,  H03M13/17

摘要： Apparatus and methods are disclosed for providing an improved system for encoding and decoding of Reed-Solomon and related codes. The system employs a k-bit-serial shift register for encoding and residue generation. For decoding, a residue is generated as data is read. Single-burst errors are corrected in real time by a k-bit-serial burst trapping decoder that operates on this residue. Error cases greater than a single burst are corrected with a non-real-time firmware decoder, which retrieves the residue and converts it to a remainder, then converts the remainder to syndromes, and then attempts to compute error locations and values from the syndromes. In the preferred embodiment, a new low-order first, k-bit-serial, finite field constant multiplier is employed within the burst trapping circuit. Also, code symbol sizes are supported that need not equal the information byte size. The implementor of the methods disclosed may choose time-efficient or space-efficient firmware for multiple-burst correction.

摘要翻译： 公开了用于提供用于对Reed-Solomon和相关代码进行编码和解码的改进系统的装置和方法。 该系统采用k位串行移位寄存器进行编码和残差生成。 对于解码，在读取数据时产生残差。 单脉冲串错误通过对该残余物进行操作的k位串行突发捕获解码器实时校正。 使用非实时固件解码器校正大于单个突发的错误情况，该解码器检索残差并将其转换为余数，然后将余数转换为综合征，然后尝试计算来自综合征的错误位置和值。 在优选实施例中，在突发捕获电路内采用新的低阶第一，k位串行有限域常数乘法器。 此外，支持不需要等于信息字节大小的代码符号大小。 所公开的方法的实现者可以选择用于多脉冲串校正的时间效率或空间有效的固件。

公开(公告)号：US4562577A

公开(公告)日：1985-12-31

申请号：US533828

申请日：1983-09-19

申请人： Neal Glover ,  Michael J. O'Keeffe ,  S. Robert Perera

发明人： Neal Glover ,  Michael J. O'Keeffe ,  S. Robert Perera

IPC分类号： G11B20/18 ,  H03M13/15 ,  G06F11/10

CPC分类号： G11B20/1833 ,  H03M13/15

摘要： A shared encoder/decoder circuit for use with a Reed-Solomon coding scheme of an optical disk storage system. The optical disk system includes a drive adapted to permanently store data on a removable platter. Prior to recording a data byte on the platter, the data is encoded with a Reed-Solomon code. When the data is read from the disk, it is decoded and error correction syndromes are generated. The same circuitry is shared for performing the encoding and decoding functions. This circuitry includes independent sets of a RAM, coupled to one input of an exclusive OR (modulo two sum) adding circuit. The output of the adding circuit is fed back to an input to the RAM. Two multiplier circuits are coupled to the output of the RAM. A product of one is tied to one input of the modulo two addition circuit. The product of the other is combined with similar products from other sets, and the resulting combination signal is selectively connected to the other input of the modulo two addition circuit, along with data to be recorded on the platter, or data read from the platter.

摘要翻译： 一种用于光盘存储系统的Reed-Solomon编码方案的共享编码器/解码器电路。 光盘系统包括适于将数据永久存储在可移动盘片上的驱动器。 在盘片上记录数据字节之前，用Reed-Solomon码对数据进行编码。 当从磁盘读取数据时，它被解码并产生纠错综合征。 共享相同的电路用于执行编码和解码功能。 该电路包括独立的一组RAM，耦合到异或（模二和）加法电路的一个输入。 加法电路的输出反馈到RAM的输入。 两个乘法器电路耦合到RAM的输出。 一个乘积被连接到模二加法电路的一个输入端。 另一个的产品与来自其他集合的类似产品组合，并且所得到的组合信号被选择性地连接到模二加法电路的另一输入以及要记录在盘片上的数据或从盘片读取的数据。

公开(公告)号：US20080285549A1

公开(公告)日：2008-11-20

申请号：US12126188

申请日：2008-05-23

申请人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

发明人： Richard T. Behrens ,  Kent D. Anderson ,  Alan J. Armstrong ,  Trent Dudley ,  Bill R. Foland ,  Neal Glover ,  Larry D. King

IPC分类号： H04L12/50

CPC分类号： G11B20/10055 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/1258 ,  G11B20/1403 ,  G11B20/1426 ,  G11B20/18 ,  G11B27/3027 ,  G11B2020/1476 ,  H03M13/31

摘要： A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

摘要翻译： 公开了具有提供数字增益控制，定时恢复，均衡，数字峰值检测，序列检测，RLL（1,7）编码和解码，容错同步和信道质量测量的单芯片集成电路数字部分的同步读通道 。 集成电路既适用于中心采样和侧采样，又具有各种脉冲整形和恢复参数的高度可编程性，以及使用序列检测或数字峰值检测提供解码数据的能力。 这些特征以及容错同步标记检测以及当同步标记被消除时恢复数据的能力允许各种各样的重试和恢复策略以最大化数据恢复的可能性。 公开了包括在单个集成电路中并入模拟功能以及读取通道的主要数字功能的实施例的各种实施例，以及利用支持大类部分响应通道的降低复杂度的可编程修改维特比检测器的优选实施例。