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1.发明申请公开(公告)号：US20100257340A1
公开(公告)日：2010-10-07
申请号：US12417798
申请日：2009-04-03
申请人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James A. Van Norstrand, JR.
发明人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James A. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853
摘要： Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.
摘要翻译： 公开了一种用于将处理器指令分组以由处理器执行的方法和系统，其中处理器指令组包括至少两个分支处理器指令。 在一个或多个实施例中，指令缓冲器可以通过在指令缓冲器中存储获取的处理器指令直到所读出的处理器指令准备解码，从而将指令提取操作与指令解码操作分离。 组形成可以涉及从指令缓冲器中移除处理器指令并将处理器指令路由到将处理器指令传送给解码器的锁存器。 在单个时钟周期内从指令缓冲区中删除的处理器指令可以称为一组处理器指令。 在一个或多个实施例中，组中的第一指令必须是指令缓冲器中的最早的指令，并且必须从从最老到最小的指令缓冲器中移除指令。
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公开(公告)号：US08127115B2
公开(公告)日：2012-02-28
申请号：US12417798
申请日：2009-04-03
申请人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James Albert Van Norstrand, Jr.
发明人： Richard William Doing , Kevin Neal Magil , Balaram Sinharoy , Jeffrey R. Summers , James Albert Van Norstrand, Jr.
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853
摘要： Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions. In one or more embodiments, an instruction buffer can decouple an instruction fetch operation from an instruction decode operation by storing fetched processor instructions in the instruction buffer until the fetched processor instructions are ready to be decoded. Group formation can involve removing processor instructions from the instruction buffer and routing the processor instruction to latches that convey the processor instructions to decoders. Processor instructions that are removed from instruction buffer in a single clock cycle can be called a group of processor instructions. In one or more embodiments, the first instruction in the group must be the oldest instruction in the instruction buffer and instructions must be removed from the instruction buffer ordered from oldest to youngest.
摘要翻译： 公开了一种用于将处理器指令分组以由处理器执行的方法和系统，其中处理器指令组包括至少两个分支处理器指令。 在一个或多个实施例中，指令缓冲器可以通过在指令缓冲器中存储获取的处理器指令直到所读出的处理器指令准备解码，从而将指令提取操作与指令解码操作分离。 组形成可以涉及从指令缓冲器中移除处理器指令并将处理器指令路由到将处理器指令传送给解码器的锁存器。 在单个时钟周期内从指令缓冲区中删除的处理器指令可以称为一组处理器指令。 在一个或多个实施例中，组中的第一指令必须是指令缓冲器中的最早的指令，并且必须从从最老到最小的指令缓冲器中移除指令。
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公开(公告)号：US20100262806A1
公开(公告)日：2010-10-14
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译： 在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。 这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。 所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。 此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。
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4.发明授权Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches 失效用于动态管理非预测分支的指令缓冲区深度的方法和装置公开(公告)号：US07779232B2
公开(公告)日：2010-08-17
申请号：US11845838
申请日：2007-08-28
申请人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
发明人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
CPC分类号： G06F9/3804
摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
摘要翻译： 用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。 分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。 缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。 替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径 。
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公开(公告)号：US08131976B2
公开(公告)日：2012-03-06
申请号：US12422595
申请日：2009-04-13
申请人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
发明人： Richard W. Doing , Susan E. Eisen , David S. Levitan , Kevin N. Magill , Brian R. Mestan , Balaram Sinharoy , Benjamin W. Stolt , Jeffrey R. Summers , Albert J. Van Norstrand, Jr.
CPC分类号： G06F9/3802 , G06F9/322 , G06F9/3806 , G06F9/3853 , G06F9/3855 , G06F9/3861
摘要： Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.
摘要翻译： 在数据处理系统中提供用于通过数据处理系统的处理器流水线跟踪有效地址的机制。 这些机制包括用于从指令高速缓存取出指令的逻辑，并通过数据处理系统中的有效地址表逻辑将有效地址表（EAT）数据结构中的条目与获取的指令相关联。 所述机制还包括用于将有效地址标签（eatag）与所述获取的指令相关联的逻辑，所述标签包括指向所述EAT中的条目的基本食品，以及食品标签偏移量。 此外，这些机制包括通过处理eatag来处理通过处理器管线的指令的逻辑。
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6.发明申请Method and Apparatus for Dynamically Managing Instruction Buffer Depths for Non-Predicted Branches 失效用于动态管理非预测分支的指令缓冲区深度的方法和装置公开(公告)号：US20090063819A1
公开(公告)日：2009-03-05
申请号：US11845838
申请日：2007-08-28
申请人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
发明人： Richard W. Doing , Michael O. Klett , Kevin N. Magill , Brian R. Mestan , David Mui , Balaram Sinharoy , Jeffrey R. Summers
CPC分类号： G06F9/3804
摘要： A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allocated for storing predicted branch instruction streams and another portion, which may be zero-sized during high prediction confidence conditions, is allocated to the non-predicted branch instruction stream. The size of the buffers is adjusted dynamically in conformity with an on-going prediction confidence that provides a measure of how well branch prediction mechanisms are working for a given instruction thread. An alternate instruction fetch address table can be maintained and multiplexed with the main fetch address register for addressing the instruction cache, so that the instruction stream can be quickly shifted to the non-predicted path when a branch instruction is resolved to the non-predicted path.
摘要翻译： 用于动态管理非预测分支的指令缓冲器深度的方法和装置减少与低置信度分支预测条件相关联的浪费的能量和资源。 分配用于指令线程的指令缓冲器的一部分用于存储预测的分支指令流，并且在高预测置信度条件下可以为零大小的另一部分被分配给非预测分支指令流。 缓冲区的大小根据正在进行的预测置信度动态调整，提供了分支预测机制对给定指令线程的工作原理的测量。 替代指令提取地址表可以与主提取地址寄存器保持多路复用，用于对指令高速缓存进行寻址，使得当分支指令被解析为非预测路径时，可以将指令流快速移位到非预测路径 。
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公开(公告)号：US20100262813A1
公开(公告)日：2010-10-14
申请号：US12423608
申请日：2009-04-14
申请人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
发明人： Mary D. Brown , Richard W. Doing , Kevin N. Magill , Brian R. Mestan , Wolfram M. Sauer , Balaram Sinharoy , Jeffrey R. Summers , Albert J. Van Norstrand, JR.
IPC分类号： G06F9/38
CPC分类号： G06F9/30003 , G06F8/433 , G06F9/30058 , G06F9/30072 , G06F9/3017 , G06F9/30174 , G06F9/3844 , G06F9/3846 , G06F9/3855
摘要： Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.
摘要翻译： 在处理器中提供用于检测和处理短前进分支转换候选的机制。 机制识别计算机代码中的条件分支，并确定短向前向条件分支是否要转换为非分支条件指令序列。 此外，机制将条件分支转换为包括解决指令和取决于解析指令的一个或多个条件指令的非分支条件指令序列。 此外，这些机制代替计算机代码中的条件分支执行非分支条件指令序列，并且基于非分支条件指令序列的执行生成计算机代码的输出。
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公开(公告)号：US08707016B2
公开(公告)日：2014-04-22
申请号：US12024211
申请日：2008-02-01
IPC分类号： G06F9/30
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. The set of helper thread binaries and the set of main thread binaries are partitioned according to common instruction boundaries. As a first partition in the set of main thread binaries executes within a first core, a second partition in the set of helper thread binaries executes within a second core, thus “warming up” the cache in the second core. When the first partition of the main completes execution, a second partition of the main core moves to the second core, and executes using the warmed up cache in the second core.
摘要翻译： 创建一组辅助线程二进制文件来检索一组主线程二进制文件使用的数据。 辅助线程二进制文件集和主线程二进制文件集合根据公共指令边界进行分区。 作为主线程二进制文件集合中的第一分区在第一核心内执行，该辅助线程二进制文件集中的第二分区在第二核心内执行，从而“预热”第二核心中的高速缓存。 当主要的第一分区完成执行时，主核心的第二分区移动到第二核心，并使用第二核心中的预热高速缓存执行。
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公开(公告)号：US08612730B2
公开(公告)日：2013-12-17
申请号：US12796124
申请日：2010-06-08
申请人： Ronald P. Hall , Venkat Rajeev Indukuru , Alexander Erik Mericas , Balaram Sinharoy , Zhong Liang Wang
发明人： Ronald P. Hall , Venkat Rajeev Indukuru , Alexander Erik Mericas , Balaram Sinharoy , Zhong Liang Wang
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/327 , G06F11/3466 , G06F2201/865 , G06F2201/88
摘要： A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an assist thread. The processor selects the at least one secondary thread from the set of secondary threads to become the assist thread in response to a determination that the at least one secondary thread of the set of secondary threads is available for use as an assist thread. The processor changes profiling of running of instructions in the program from the main thread to the assist thread.
摘要翻译： 一种用于管理程序中的指令的运行的方法和数据处理系统。 数据处理系统的处理器接收监视单元的监视指令。 处理器确定一组辅助线程的至少一个辅助线程是否可用作辅助线程。 响应于确定所述一组次要线程的至少一个辅助线程可用作辅助线程，所述处理器从所述辅助线程组中选择所述至少一个辅助线程以成为所述辅助线程。 处理器将程序中指令的运行情况从主线程更改为辅助线程。
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公开(公告)号：US08387065B2
公开(公告)日：2013-02-26
申请号：US12425343
申请日：2009-04-16
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/3842
摘要： A method and a data processing system by which population count (popcount) operations are efficiently performed without incurring the latency and loss of critical processing cycles and bandwidth of real time processing. The method comprises: identifying data to be stored to memory for which a popcount may need to be determined; speculatively performing a popcount operation on the data as a background process of the processor while the data is being stored to memory; storing the data to a first memory location; and storing a value of the popcount generated by the popcount operation within a second memory location. The method further comprises: determining a size of data; determining a granular level at which the popcount operation on the data will be performed; and reserving a size of said second memory location that is sufficiently large to hold the value of the popcount.
摘要翻译： 一种方法和数据处理系统，通过该方法和数据处理系统有效地执行人口计数（popcount）操作，而不会导致关键处理周期的延迟和丢失以及实时处理的带宽。 该方法包括：识别要存储到可能需要确定一个弹出窗口的存储器的数据; 在将数据存储到存储器中的情况下，作为处理器的后台处理推测性地对数据进行弹出数据操作; 将数据存储到第一存储器位置; 以及将由所述popcount操作生成的所述popcount的值存储在第二存储器位置内。 该方法还包括：确定数据的大小; 确定将执行对数据的弹出数据操作的粒度级别; 以及保留所述第二存储器位置的大小足够大以保持所述用户名的值。
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