公开(公告)号：US20150109060A1

公开(公告)日：2015-04-23

申请号：US14244948

申请日：2014-04-04

Applicant: RICHTEK TECHNOLOGY CORP

Inventor： Yen-Yin Huang ,  Ming-Shih Yu

IPC: H03L7/085

CPC classification number: H03L1/00

Abstract: A process, voltage, and temperature compensated oscillator, formed on an integrate circuit implemented by a semiconductor process, receives a supply voltage and includes: a variation bias unit provided with a variation bias output terminal and generating a process, voltage, and temperature compensated signal; a controlled oscillating unit provided with a control input terminal and an oscillating output and determining a signal oscillating frequency at the oscillating output terminal according to a signal at the control input terminal; and a tuning unit provided with a tuning input terminal, a compensating input terminal, a control output terminal, and a variable-parameter element, wherein the variable-parameter element includes a parameter and is coupled to the control output terminal, and the tuning unit determines the parameter according to a signal at the variation bias output terminal and a voltage signal or a digital signal received at the tuning input terminal.

Abstract translation: 形成在由半导体工艺实现的集成电路上的工艺，电压和温度补偿振荡器接收电源电压，并包括：设置有变化偏置输出端子并产生过程，电压和温度补偿信号的变化偏置单元 ; 控制振荡单元，设置有控制输入端子和振荡输出端，并根据控制输入端子处的信号确定振荡输出端子处的信号振荡频率; 以及设置有调谐输入端子，补偿输入端子，控制输出端子和可变参数元件的调谐单元，其中所述可变参数元件包括参数并耦合到所述控制输出端子，并且所述调谐单元 根据变化偏置输出端子处的信号和在调谐输入端子处接收的电压信号或数字信号来确定参数。

公开(公告)号：US08917806B1

公开(公告)日：2014-12-23

申请号：US14256031

申请日：2014-04-18

Applicant: Richtek Technology Corp

Inventor： Yen-Yin Huang ,  Kuo-Shih Tsai ,  Ming-Shih Yu

IPC: H03D3/24 ,  H04L7/033

CPC classification number: H04L7/0331 ,  H03L2207/50

Abstract: A phase/frequency detector module, applicable to a digital phase-locked loop, includes: an edge detector for receiving a reference clock signal and a counting clock signal, where when a positive edge of the counting clock signal occurs, if a positive edge of the reference clock signal has occurred, the edge detector outputs an edge-detected signal, else the edge detector outputs an edge-not-detected signal; a counter coupled to the edge detector, where if receiving the edge-detected signal, the counter outputs a counting result forming a frequency error signal, resets, and loads a count value, and if receiving the edge-not-detected signal, the counter continues to count on the positive edge of the counting clock signal; and a frequency phase converter for performing integration over the counting result, where the integral forms a phase error signal.

Abstract translation: 适用于数字锁相环的相位/频率检测器模块包括：边缘检测器，用于接收参考时钟信号和计数时钟信号，其中当计数时钟信号的上升沿出现时，如果 参考时钟信号发生，边缘检测器输出边沿检测信号，否则边沿检测器输出未检测到边沿的信号; 耦合到边缘检测器的计数器，其中如果接收到边沿检测信号，则计数器输出形成频率误差信号的计数结果，复位并加载计数值，并且如果接收到未被检测的边缘信号，则计数器 继续依靠计数时钟信号的上升沿; 以及用于对计数结果执行积分的频率相位转换器，其中积分形成相位误差信号。