公开(公告)号：US5555392A

公开(公告)日：1996-09-10

申请号：US130284

申请日：1993-10-01

申请人： Robert B. Chaput ,  Randy L. Steck

发明人： Robert B. Chaput ,  Randy L. Steck

IPC分类号： G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0859

摘要： A method and apparatus for providing a non-blocking cache that uses substantially less die area than a prior art non-blocking cache. In the present invention, pending count and ignore fill fields are added to each line of the cache. These fields are used in conjunction with a valid field (that indicates whether or not the line contains valid data) to keep track of the status of pending load operations that have resulted in cache misses. The pending field keeps a count of the number of outstanding load misses for the line. If a store occurs for an address of a line, the ignore fill field is set to indicate that any fills that are pending for the line are to be ignored because the pending fills will be supplying stale data to the line.

摘要翻译： 一种用于提供使用比现有技术的非阻塞高速缓存大大减少管芯面积的非阻塞高速缓存的方法和装置。 在本发明中，待处理的计数和忽略填充字段被添加到高速缓存的每一行。 这些字段与有效字段（表示行是否包含有效数据）一起使用，以跟踪导致高速缓存未命中的待处理加载操作的状态。 待处理字段保留该行未完成的加载缺失数量的计数。 如果对于一行的地址发生存储，则忽略填充字段被设置为指示该行待处理的任何填充将被忽略，因为待处理的填充将向该行提供过时的数据。

公开(公告)号：US06374350B1

公开(公告)日：2002-04-16

申请号：US09584890

申请日：2000-06-01

申请人： Reynold V. D'Sa ,  Rebecca E. Hebda ,  Stavros Kalafatis ,  Alan B. Kyker ,  Robert B. Chaput

发明人： Reynold V. D'Sa ,  Rebecca E. Hebda ,  Stavros Kalafatis ,  Alan B. Kyker ,  Robert B. Chaput

IPC分类号： G06F942

CPC分类号： G06F9/3806 ,  G06F9/30054

摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.

摘要翻译： 提供微处理器中的指令流水线。 指令流水线包括多个流水线单元，多个流水线单元中的每一个处理多个指令。 多个流水线单元中的至少两个是流水线的至少一些指令的源。 该流水线还包括至少两个推测返回地址堆栈，每个耦合的推测返回地址栈耦合到至少一个指令源单元。 每个推测返回地址堆栈都能够存储至少两个推测返回地址。

公开(公告)号：US6151671A

公开(公告)日：2000-11-21

申请号：US27407

申请日：1998-02-20

申请人： Reynold V. D'Sa ,  Rebecca E. Hebda ,  Stavros Kalafatis ,  Alan B. Kyker ,  Robert B. Chaput

发明人： Reynold V. D'Sa ,  Rebecca E. Hebda ,  Stavros Kalafatis ,  Alan B. Kyker ,  Robert B. Chaput

IPC分类号： G06F9/38 ,  G06F9/42

CPC分类号： G06F9/3806 ,  G06F9/30054

摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.