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1.发明授权System and method of maintaining and utilizing multiple return stack buffers 失效维护和利用多个返回堆栈缓冲区的系统和方法公开(公告)号：US06374350B1
公开(公告)日：2002-04-16
申请号：US09584890
申请日：2000-06-01
IPC分类号： G06F942
CPC分类号： G06F9/3806 , G06F9/30054
摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.
摘要翻译： 提供微处理器中的指令流水线。 指令流水线包括多个流水线单元，多个流水线单元中的每一个处理多个指令。 多个流水线单元中的至少两个是流水线的至少一些指令的源。 该流水线还包括至少两个推测返回地址堆栈，每个耦合的推测返回地址栈耦合到至少一个指令源单元。 每个推测返回地址堆栈都能够存储至少两个推测返回地址。
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公开(公告)号：US6151671A
公开(公告)日：2000-11-21
申请号：US27407
申请日：1998-02-20
CPC分类号： G06F9/3806 , G06F9/30054
摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the plurality of pipeline units processing a plurality of instructions. At least two of the plurality of pipeline units are a source of at least some of the instructions for the pipeline. The pipeline further includes at least two speculative return address stacks, each of the speculative return address stacks coupled is coupled to at least one of the instruction source units. Each of the speculative return return address stacks are capable of storing at least two speculative return addresses.
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3.发明授权System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units 失效用于通过多个存储设备和流水线单元处理多个分支指令的系统和方法
公开(公告)号：US6055630A
公开(公告)日：2000-04-25
申请号：US63205
申请日：1998-04-20
申请人： Reynold V. D'Sa , Alan B. Kyker , Gad S. Sheaffer , Gustavo P. Espinosa , Stavros Kalafatis , Rebecca E. Hebda
发明人： Reynold V. D'Sa , Alan B. Kyker , Gad S. Sheaffer , Gustavo P. Espinosa , Stavros Kalafatis , Rebecca E. Hebda
CPC分类号： G06F9/3808 , G06F9/3802 , G06F9/3806 , G06F9/3844 , G06F9/3863 , G06F9/3867
摘要： An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including branch instructions. The instruction pipeline further includes a plurality of storage device which store a respective branch information data. Each of the storage devices are associated with at least one of pipeline units. Each respective branch information data is determined as a function of at least one of the branch instructions processed. Two of the pipeline units include branch prediction circuitry for predicting branch direction as a function of the stored branch information data.
摘要翻译： 提供微处理器中的指令流水线。 指令流水线包括多个流水线单元，每个流水线单元处理包含分支指令的多个指令。 指令流水线还包括存储各个分支信息数据的多个存储装置。 每个存储设备与管道单元中的至少一个相关联。 根据所处理的分支指令中的至少一个来确定各个分支信息数据。 两个流水线单元包括用于根据存储的分支信息数据预测分支方向的分支预测电路。
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4.发明授权Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information table 失效使用指令序列号索引状态信息表从回写阶段事件信号或微分支错误预测中恢复公开(公告)号：US06493821B1
公开(公告)日：2002-12-10
申请号：US09094027
申请日：1998-06-09
IPC分类号： G06F938
CPC分类号： G06F9/30174 , G06F9/3863
摘要： A pipelined microprocessor is provided. The pipelined microprocessor includes a writeback stage which signals an event and sends a sequence number of an instruction which had the event. The event may be, for example, a fault, a trap or a branch misprediction. The pipelined microprocessor further includes a decode stage which stores recovering state information for respective instructions and is responsive to the writeback stage signaling the event by using the sequence number to access the stored information to retrieve recovery state information of the instruction which had the event. The recovery state information may include, for example, a pointer to a next linear instruction, a pointer to a branch target instruction, a branch prediction, or an instruction source. Event recovery micro-code determines a next instruction to execute using the recovery state information, the next instruction being executed after a machine recovery.
摘要翻译： 提供流水线微处理器。 流水线微处理器包括回写阶段，其向事件发信号并发送具有该事件的指令的序列号。 事件可能是例如故障，陷阱或分支错误预测。 流水线微处理器还包括解码级，其存储相应指令的恢复状态信息，并且响应于写回级，通过使用序列号来访问存储的信息以检索具有该事件的指令的恢复状态信息来发信号通知该事件。 恢复状态信息可以包括例如指向下一个线性指令的指针，指向分支目标指令的指针，分支预测或指令源。 事件恢复微码确定使用恢复状态信息执行的下一条指令，下一条指令在机器恢复后执行。
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公开(公告)号：US07334115B1
公开(公告)日：2008-02-19
申请号：US09608512
申请日：2000-06-30
申请人： Reynold V. D'Sa , Alan B. Kyker , Slade A. Morgan , Rebecca E. Hebda , Richard A. Weier , Robert F. Krick
发明人： Reynold V. D'Sa , Alan B. Kyker , Slade A. Morgan , Rebecca E. Hebda , Richard A. Weier , Robert F. Krick
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3017 , G06F9/3808 , G06F9/3861
摘要： The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro instruction, are stored in a decoded micro-op cache. Branch prediction logic determines whether a branch is bogus or not. If the branch taken was determined to be bogus, the present invention causes the micro-ops which descend from the original bogus branch micro-op instruction to be flagged and subsequently moved to the back-end of the processor for retirement. Further, the branch prediction logic (the branch prediction logic storage buffer) is updated as to what the actual direction of the branch was. In this manner then, bogus branches are detected, recovered from and further prevented.
摘要翻译： 本发明提供了一种用于检测和预防微处理器中的虚假分支预测和恢复的方法和装置。 从宏指令解码的微操作被存储在解码的微操作高速缓存中。 分支预测逻辑确定分支是否为假。 如果所采取的分支被确定为假的，则本发明使得从原始虚假分支微操作指令下降的微操作被标记并随后移动到处理器的后端退休。 此外，分支预测逻辑（分支预测逻辑存储缓冲器）被更新为分支的实际方向是什么。 以这种方式，则检测到虚假的分支，从中进一步预防和恢复。
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6.发明授权Apparatus having a micro-instruction queue, a micro-instruction pointer programmable logic array and a micro-operation read only memory and method for use thereof 失效具有微指令队列，微指令指针可编程逻辑阵列和微操作只读存储器及其使用方法的装置公开(公告)号：US07519799B2
公开(公告)日：2009-04-14
申请号：US10714674
申请日：2003-11-18
CPC分类号： G06F9/30145 , G06F9/28 , G06F9/3822
摘要： Embodiments of the present invention relate to high-performance processors, and more specifically, to processors that store all operation information associated with each instruction in a single memory. A processor including multiple programmable logic arrays (PLAs); an instruction pointer queue coupled to the multiple PLAs; and an instruction pointer sequencing logic/predictor component coupled to the instruction pointer queue. The processor further includes a micro-operation cache coupled to the instruction pointer sequencing logic/predictor component; a micro-operation memory coupled to the micro-operation cache; and a trace pipe (TPIPE) coupled to the micro-operation cache and the instruction pointer queue.
摘要翻译： 本发明的实施例涉及高性能处理器，更具体地，涉及将与每个指令相关联的所有操作信息存储在单个存储器中的处理器。 一种包括多个可编程逻辑阵列（PLA）的处理器; 耦合到所述多个PLA的指令指针队列; 以及耦合到指令指针队列的指令指针序列逻辑/预测器组件。 处理器还包括耦合到指令指针排序逻辑/预测器组件的微操作高速缓存器; 耦合到微操作高速缓存的微操作存储器; 以及耦合到微操作高速缓存和指令指针队列的跟踪管（TPIPE）。
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