公开(公告)号：US10793430B2

公开(公告)日：2020-10-06

申请号：US16131455

申请日：2018-09-14

Applicant: Robert Bosch GmbH

Inventor： Sebastien Loiseau ,  Arnim Hoechst ,  Bernhard Gehl ,  Eugene Moliere Tanguep Njiokep ,  Sandra Altmannshofer

IPC: B81C1/00

Abstract: A method for producing thin MEMS wafers including: (A) providing an SOI wafer having an upper silicon layer, a first SiO2 layer and a lower silicon layer, the first SiO2 layer being situated between the upper silicon layer and the lower silicon layer, (B) producing a second SiO2 layer on the upper silicon layer, (C) producing a MEMS structure on the second SiO2 layer, (D) introducing clearances into the lower silicon layer down to the first SiO2 layer, (E) etching the first SiO2 layer and thus removing the lower silicon layer.

公开(公告)号：US20190092631A1

公开(公告)日：2019-03-28

申请号：US16131455

申请日：2018-09-14

Applicant: Robert Bosch GmbH

Inventor： Sebastien Loiseau ,  Arnim Hoechst ,  Bernhard Gehl ,  Eugene Moliere Tanguep Njiokep ,  Sandra Altmannshofer

IPC: B81C1/00

CPC classification number: B81C1/00476 ,  B81C1/00158 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/056

Abstract: A method for producing thin MEMS wafers including: (A) providing an SOI wafer having an upper silicon layer, a first SiO2 layer and a lower silicon layer, the first SiO2 layer being situated between the upper silicon layer and the lower silicon layer, (B) producing a second SiO2 layer on the upper silicon layer, (C) producing a MEMS structure on the second SiO2 layer, (D) introducing clearances into the lower silicon layer down to the first SiO2 layer, (E) etching the first SiO2 layer and thus removing the lower silicon layer.