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公开(公告)号：US6014709A
公开(公告)日：2000-01-11
申请号：US964606
申请日：1997-11-05
IPC分类号： G06F12/08 , G06F15/167 , G06F15/173 , G06F13/00
CPC分类号： G06F15/17375
摘要： System and method for controlling the flow of messages in a computer system to minimize congestion and prevent deadlocks in communications. The computer system includes a main memory, a plurality of crossbar switches, a plurality of third level caches, and a plurality of input/output modules, which are interconnected via the communications network of the computer system. System and method prevents deadlocks between input/output modules and main memory, and between processors and main memory caused by data needed for making forward progress in processing being trapped behind messages. System and method utilize control signals and auxiliary buffers to hold and redirect messages out of the path of data so that data may flow to the input/output modules and processors when needed, and messages may flow when convenient.
摘要翻译： 用于控制计算机系统中的消息流的系统和方法，以最小化拥塞并防止通信中的死锁。 计算机系统包括经由计算机系统的通信网络互连的主存储器，多个交叉开关，多个第三级高速缓存和多个输入/输出模块。 系统和方法可以防止输入/输出模块与主存储器之间以及处理器与主存储器之间的死锁，这些数据是由处理中被捕获的信息所需的数据所需的。 系统和方法利用控制信号和辅助缓冲器来保存和重定向数据路径中的消息，以便在需要时数据可能流向输入/输出模块和处理器，并且消息可以在方便时流动。
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2.发明授权Directory-based cache coherency system supporting multiple instruction processor and input/output caches 失效基于目录的高速缓存一致性系统支持多指令处理器和输入/输出缓存公开(公告)号：US06587931B1
公开(公告)日：2003-07-01
申请号：US09001598
申请日：1997-12-31
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0886 , G06F2212/621
摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.
摘要翻译： 公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。 该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。 该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。 通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。 该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。 高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。 根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。 相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。 一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。
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3.发明授权
公开(公告)号：US6049845A
公开(公告)日：2000-04-11
申请号：US964630
申请日：1997-11-05
IPC分类号： G06F13/18 , G06F12/08 , G06F13/16 , G06F13/362 , G06F15/167 , G06F13/00
CPC分类号： G06F13/1605
摘要： A system and method for optimizing the amount of time it takes for a requestor (device) to receive data from a memory storage unit in a multi-requestor bus environment. The present invention provides a unidirectional response signal, referred to as an early warning signal, sent from a memory storage unit to a device, sometime after that device has executed a fetch request for data, to alert the device that the data is forthcoming. This early warning signal allows the device to arbitrate for the data bus so that when the data arrives, the device will have exclusive ownership of the data bus to accept the data immediately. The present invention comprises a main memory, a cache memory, one or more processor modules, one or more I/O modules, and an early warning bus. The cache memory is connected to the main memory via an interface bus. The processor modules are connected to the cache memory via a processor interface bus. The I/O modules are connected to the main memory via an I/O interface bus. Both the processor modules and the I/O modules include means for requesting a data unit from the main memory. The early warning bus is connected between the main memory, the cache memory, and the I/O module.
摘要翻译： 一种用于优化请求者（设备）从多请求者总线环境中的存储器存储单元接收数据所需的时间量的系统和方法。 本发明提供了一种从存储器存储单元发送到设备的称为早期警告信号的单向响应信号，该设备在该设备执行了对数据的取出请求之后的某个时刻向该设备通知数据即将到来。 该预警信号允许设备对数据总线进行仲裁，以便当数据到达时，设备将具有数据总线的独占所有权以立即接受数据。 本发明包括主存储器，高速缓冲存储器，一个或多个处理器模块，一个或多个I / O模块和预警总线。 高速缓存通过接口总线连接到主存储器。 处理器模块通过处理器接口总线连接到高速缓冲存储器。 I / O模块通过I / O接口总线连接到主存储器。 处理器模块和I / O模块都包括用于从主存储器请求数据单元的装置。 预警总线连接在主存储器，高速缓冲存储器和I / O模块之间。
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4.发明授权Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks 失效计算机系统包括多个高速缓存，并且利用访问历史或模式来确定用于有效处理软件锁的数据所有权
公开(公告)号：US6052760A
公开(公告)日：2000-04-18
申请号：US964626
申请日：1997-11-05
CPC分类号： G06F12/0811 , G06F12/0817
摘要： A system and method for enabling a multiprocessor system employing a memory hierarchy to identify data units or locations being used as software locks. The memory hierarchy comprises a main memory having a plurality of data units, a plurality of caches that operate independently of each other, and at least one coherent domain interfaced to each cache. Each coherent domain comprises at least two processors. The main memory maintains coherency of data among the plurality of caches using a directory that maintains information about each data line. The system of the present invention allows a requesting agent, such as a processor or cache, to request a data unit without specifying the type of ownership, where ownership may be exclusive or shared. The directory includes history information that defines the previous access pattern of the requested data unit. Prior to forwarding the requested data unit to the requesting agent, the main memory checks, using a conditional fetch command, the history information to determine what type of ownership to associate with the requested data unit. The requested data unit is then delivered to the requesting agent with ownership rights specified by the history information. The processors may utilize a directory-based protocol such as MESI (modified, exclusive, shared, invalid) to maintain coherence among the processors, with each processor snooping a shared bus to track the status of caches lines in the other processors.
摘要翻译： 一种用于使得采用存储器层次结构的多处理器系统能够识别用作软件锁的数据单元或位置的系统和方法。 存储器层级包括具有多个数据单元的主存储器，彼此独立地操作的多个高速缓存以及与每个高速缓存接口的至少一个相干域。 每个相干域包括至少两个处理器。 主存储器使用维护关于每个数据线的信息的目录来保持多个高速缓存之间的数据的一致性。 本发明的系统允许诸如处理器或高速缓存的请求代理请求数据单元而不指定所有权的类型，其中所有权可以是独占的或共享的。 该目录包括定义所请求数据单元的先前访问模式的历史信息。 在将所请求的数据单元转发到请求代理之前，主存储器使用条件获取命令来检查历史信息以确定与请求的数据单元相关联的所有权类型。 所请求的数据单元然后被传递给具有由历史信息指定的所有权的请求代理。 处理器可以使用诸如MESI（经修改，排他，共享，无效）的基于目录的协议来维持处理器之间的一致性，每个处理器窥探共享总线以跟踪其他处理器中的高速缓存行的状态。
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5.发明授权Directory based cache coherency system supporting multiple instruction processor and input/output caches 有权基于目录的高速缓存一致性系统支持多指令处理器和输入/输出缓存公开(公告)号：US06438659B1
公开(公告)日：2002-08-20
申请号：US09645233
申请日：2000-08-24
IPC分类号： G06F1208
CPC分类号： G06F12/0817 , G06F12/0886 , G06F2212/621
摘要： A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/0) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line. The cache line states are used to implement a state machine which tracks the cache lines and ensures only valid copies of are maintained within the memory system. According to another aspect of the system, the main memory performs continuous tracking and control functions for all cache lines residing in the IP caches. In contrast, the system maintains tracking and control functions for only predetermined cache lines provided to the I/O units so that system overhead may be reduced. The coherency system further supports multiple heterogeneous instruction processors which operate on cache lines of different sizes.
摘要翻译： 公开了一种基于目录的高速缓存一致性系统，用于具有通过共享主存储器耦合的多个指令处理器（IP）和多个输入/输出（I / O）单元的数据处理系统。 该系统包括一个或多个IP高速缓冲存储器，每个IP缓存存储器分别耦合到一个或多个IP和共享主存储器，用于高速缓存被称为高速缓存线的数据单元。 该系统还包括一个或多个I / O单元内的I / O存储器，每个I / O存储器耦合到共享主存储器，用于存储从共享主存储器检索的高速缓存线。 通过使用存储系统中每个缓存行的状态的中央目录来维护一致性。 该状态表示IP高速缓存和具有给定高速缓存行的有效副本的I / O存储器的身份，并进一步标识与高速缓存行相关联的一组访问权限，即高速缓存行“状态”。 高速缓存行状态用于实现跟踪高速缓存行的状态机，并且仅确保在存储器系统内维护的有效副本。 根据系统的另一方面，主存储器对驻留在IP高速缓存中的所有高速缓存行执行连续跟踪和控制功能。 相比之下，系统仅为提供给I / O单元的预定高速缓存行维护跟踪和控制功能，从而可以减少系统开销。 一致性系统还支持在不同大小的高速缓存线上运行的多个异构指令处理器。
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6.发明授权System and method for performing error recovery in a data processing system having multiple processing partitions 有权用于在具有多个处理分区的数据处理系统中执行错误恢复的系统和方法公开(公告)号：US07343515B1
公开(公告)日：2008-03-11
申请号：US10954842
申请日：2004-09-30
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/0712 , G06F11/0724
摘要： A system and method is disclosed for performing error recovery in a data processing system that supports multiple processing partitions. One or more processors and I/O modules, as well as a portion of the address space of a main memory, is allocated to each partition. In this type of configuration, requests generated by units of multiple partitions are processed by the same queue and state logic of the main memory. When a failure occurs within one processing partition, one or more units are identified as being directly affected by the fault. All requests and responses from, and to, the affected units, as well as any logical residue of these requests and responses are removed from the shared memory queue and state logic in a manner that allows the other partition to continue issuing requests and responses to the memory in a normal manner that does not involve recovery operations.
摘要翻译： 公开了一种用于在支持多个处理分区的数据处理系统中执行错误恢复的系统和方法。 一个或多个处理器和I / O模块以及主存储器的地址空间的一部分被分配给每个分区。 在这种类型的配置中，由多个分区的单元生成的请求由主存储器的相同队列和状态逻辑处理。 当在一个处理分区内发生故障时，一个或多个单元被识别为直接受故障影响。 受影响单位的所有请求和响应以及这些请求和响应的任何逻辑残差都以共享内存队列和状态逻辑的方式被删除，从而允许其他分区继续发出请求和响应 记忆以不涉及恢复操作的正常方式。
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7.发明授权公开(公告)号：US07167955B1
公开(公告)日：2007-01-23
申请号：US10745372
申请日：2003-12-23
IPC分类号： G06F12/00
CPC分类号： G06F12/0817 , G06F11/1008 , G06F2212/1032
摘要： A system and method for testing and/or initializing a Directory Store in a directory-based coherent memory. In one illustrative embodiment, the directory-based coherent memory includes a Main Store for storing a number of data entries, a Directory Store for storing the directory state for at least some of the data entries in the Main Store, and a next state block for determining a next directory state for a requested data entry in response to a memory request. To provide access to the Directory Store, and in one illustrative embodiment, a selector is provided for selecting either the next directory state value provided by the next state block or another predetermined value. The other predetermined value may be, for example, a fixed data pattern, a variable data pattern, a specified value, or any other value suitable for initializing and/or testing the Directory Store. The output of the selector may be written to the Directory Store.
摘要翻译： 用于在基于目录的连贯内存中测试和/或初始化目录存储的系统和方法。 在一个说明性实施例中，基于目录的相干存储器包括用于存储多个数据条目的主存储器，用于存储主存储器中的至少一些数据条目的目录状态的目录存储器，以及下一个状态块 响应于存储器请求确定所请求的数据条目的下一目录状态。 为了提供对目录存储的访问，并且在一个说明性实施例中，提供了选择器，用于选择由下一个状态块提供的下一个目录状态值或另一个预定值。 另一个预定值可以是例如固定数据模式，可变数据模式，指定值或适用于初始化和/或测试目录库的任何其他值。 选择器的输出可能会写入目录存储。
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8.发明授权System and method for fault handling and recovery in a multi-processing system having hardware resources shared between multiple partitions 有权具有在多个分区之间共享的硬件资源的多处理系统中的故障处理和恢复的系统和方法公开(公告)号：US06594785B1
公开(公告)日：2003-07-15
申请号：US09561270
申请日：2000-04-28
申请人： Roger L. Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson , James L. DePenning , Michael L. Haupt , Donald Kalvestrand , Daniel S. Tokoly , Frederick G. Fellenser , Maria A. Liedman
发明人： Roger L. Gilbertson , Mitchell A. Bauman , Penny L. Svenkeson , James L. DePenning , Michael L. Haupt , Donald Kalvestrand , Daniel S. Tokoly , Frederick G. Fellenser , Maria A. Liedman
IPC分类号： H02H305
CPC分类号： G06F11/0772 , G06F11/0712 , G06F11/0724 , G06F11/0793
摘要： Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A support processor handles non-immediate problems and allows resetting of memory locations formerly owned by failed units.
摘要翻译： 当多处理器计算机系统的一部分变得有故障时，将特定存储器位置中毒作为过程导致即使在共享存储器区域中也能够分离由单个故障单元拥有的特定数据的能力。 也可以由非故障单元进行连续处理。 支持处理器处理非直接问题，并允许重置以前由故障单元拥有的存储器位置。
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公开(公告)号：US06477620B1
公开(公告)日：2002-11-05
申请号：US09467190
申请日：1999-12-20
申请人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
发明人： Mitchell A. Bauman , Roger L. Gilbertson , Donald R. Kalvestrand , Joseph S. Schibinger , Daniel S. Tokoly
IPC分类号： G06F1208
CPC分类号： G06F12/0813 , G06F12/0811
摘要： A data by-pass system for a hierarchical, multi-level, memory is disclosed. The by-pass system provides by-pass interfaces between storage devices located at predetermined levels within the memory hierarchy. The hierarchical memory system of the preferred embodiment includes a main memory coupled to multiple first storage devices that each stores addressable portions of data signals retrieved from the main memory. To facilitate a more efficient transfer of data between the various storage devices in the memory system, at least one by-pass interface coupling associated ones of the first storage devices is provided. Data retrieved from a target one of the first storage devices in response to a main memory request can be routed to a different requesting one of the first storage devices via the by-pass system without requiring the use of the main memory data interfaces.
摘要翻译： 公开了一种用于分级，多级存储器的数据旁路系统。 旁路系统在位于存储器层级内的预定级别的存储设备之间提供旁路接口。 优选实施例的分级存储器系统包括耦合到多个第一存储设备的主存储器，每个存储器件存储从主存储器检索的数据信号的可寻址部分。 为了便于在存储器系统中的各种存储设备之间更有效地传输数据，提供了耦合相关联的第一存储设备的至少一个旁路接口。 可以响应于主存储器请求从第一存储设备中的目标一个检索的数据经由旁路系统路由到第一存储设备中的不同请求的一个，而不需要使用主存储器数据接口。
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公开(公告)号：US06356991B1
公开(公告)日：2002-03-12
申请号：US09001390
申请日：1997-12-31
IPC分类号： G06F1206
CPC分类号： G06F12/0607 , G06F12/0292
摘要： A programmable address translation system for a modular main memory is provided. The system is implemented using one or more General Register Arrays (GRAs), wherein each GRA performs logical-to-physical address translation for a predetermined address range within the system. Predetermined bits of a logical address are used to address a GRA associated with the logical address range. Data bits read from the GRA are then substituted for the predetermined bits of the logical address to form the physical address. In this manner, non-contiguous addressable banks of physical memory may be mapped to a selectable contiguous address range. By including within the GRA Address a number N of logical address bits used to address contiguous logical addresses, an address translation mechanism is provided which may be programmed to perform between 2-way and 2N-way address interleaving. Each GRA may be re-programmed dynamically to accommodate changing memory conditions as may occur, for example, when a range of memory is logically removed from a system because of errors. Furthermore, GRA reprogramming may occur while memory operations continue within other non-associated address ranges. Additionally, address interleaving may be selected for certain ones of the address ranges, whereas a non-interleaving scheme may be selected for other address ranges.
摘要翻译： 提供了一种用于模块化主存储器的可编程地址转换系统。 该系统使用一个或多个通用寄存器阵列（GRA）实现，其中每个GRA对系统内的预定地址范围进行逻辑到物理地址转换。 使用逻辑地址的预定比特来寻址与逻辑地址范围相关联的GRA。 然后将从GRA读取的数据位代替逻辑地址的预定位以形成物理地址。 以这种方式，物理存储器的不连续可寻址组可以被映射到可选择的相邻地址范围。 通过在GRA地址内包含用于寻址连续逻辑地址的N个逻辑地址位，提供地址转换机制，其可被编程为在2路和2N路地址交错之间执行。 可以动态地重新编程每个GRA以适应可能发生的变化的存储器条件，例如当由于错误而从系统逻辑地移除存储器的范围时。 此外，当存储器操作在其他非关联地址范围内继续时，可能会发生GRA重新编程。 另外，可以针对某些地址范围来选择地址交织，而对于其他地址范围可以选择非交织方案。
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