公开(公告)号：US06310399B1

公开(公告)日：2001-10-30

申请号：US09514268

申请日：2000-02-28

申请人： Robert Feurle ,  Sabine Mandel ,  Dominique Savignac ,  Helmut Schneider

发明人： Robert Feurle ,  Sabine Mandel ,  Dominique Savignac ,  Helmut Schneider

IPC分类号： H01L2348

CPC分类号： H01L27/10885 ,  H01L23/5225 ,  H01L27/10891 ,  H01L27/10897 ,  H01L2924/0002 ,  Y10S257/907 ,  H01L2924/00

摘要： A semiconductor memory configuration includes bit lines in a bit-line plane, a further plane different from the bit-line plane, word lines, and a memory cell area adjacent the bit-line plane, some of the bit lines having a twist running alongside others of the bit lines being untwisted, pairs of the some of the bit lines with a twist each respectively defining a twist bit-line pair, the twist bit-line pair having contacts for crossing one bit line of the twist bit-line pair over another bit line of the twist bit-line pair and over the memory-cell area through the further plane, the untwisted others of the bit lines having dummy contacts leading from the bit-line plane to the further plane. The dummy contacts lead to the word-line plane to give the word lines a homogeneous environment. The further plane can be a word-line plane including the word lines. The bit lines in the twist-free area can be approximately from 150 nm to 250 nm wide, preferably 200 nm. The twist area can only include the twist of the bit lines. The bit lines in the twist area can be approximately from 250 nm to 350 nm wide, preferably, 330 nm wide. The bit lines can have spacing from 150 to 180 nm wide. The bit lines, the word lines, the contacts, and the dummy contacts can be made from copper or aluminum.

摘要翻译： 半导体存储器配置包括位线平面中的位线，不同于位线平面的另一个平面，字线和与位线平面相邻的存储单元区域，一些位线沿着一条扭转 位线中的其他位线被解捻，一些位线的对成对分别限定扭转位线对，扭转位线对具有用于使扭转位线对的一个位线交叉的触点 扭转位线对的另一个位线和通过另一个平面的存储单元区域之后，未扭绞的其它位线具有从位线平面引导到另一个平面的虚拟触点。 虚拟触点导致字线平面，使字线成为均匀的环境。 另外的平面可以是包括字线的字线平面。 无捻区域中的位线可以约为150nm至250nm宽，优选为200nm。 扭曲区域只能包括位线的扭曲。 扭转区域中的位线可以约为250nm至350nm宽，优选为330nm宽。 位线可以具有150至180nm宽的间距。 位线，字线，触点和虚拟触点可以由铜或铝制成。

公开(公告)号：US06205044B1

公开(公告)日：2001-03-20

申请号：US09510641

申请日：2000-02-22

申请人： Robert Feurle ,  Sabine Mandel ,  Helmut Schneider

发明人： Robert Feurle ,  Sabine Mandel ,  Helmut Schneider

IPC分类号： G11C506

CPC分类号： G11C7/18 ,  G11C5/025 ,  G11C5/14

摘要： A decoder connection configuration for memory chips, in which, in a dummy region of a decoder, the dummy region being caused by a bit line twist, additional plated-through holes are provided between power supply lines and the decoder. By virtue of the bit line twist, the coupling capacitance is practically halved on account of the electrical symmetry.

摘要翻译： 一种用于存储器芯片的解码器连接配置，其中在解码器的虚拟区域中，由位线扭曲引起的虚拟区域，在电源线和解码器之间提供附加的电镀通孔。 由于位线扭曲，由于电对称性，耦合电容实际上减半。