公开(公告)号：US07822835B2

公开(公告)日：2010-10-26

申请号：US11701004

申请日：2007-02-01

申请人： Robert G. Atkinson ,  William T. Blank

发明人： Robert G. Atkinson ,  William T. Blank

IPC分类号： G06F15/173 ,  G06F17/30 ,  G06F3/12

CPC分类号： H04L41/0873 ,  H04L29/06 ,  H04L41/00 ,  H04L41/0816 ,  H04L41/0856

摘要： A logically centralized physically distributed Internet protocol (IP) network-connected devices configuration is disclosed. The technology initially receives configuration information regarding an IP network-connected devices configuration. The configuration information is then disseminated to a plurality of devices coupled with the IP network-connected devices configuration. At least a portion of the IP network-connected devices configuration with a related timestamp is then stored on any of the plurality of devices having a datastore thereon. In so doing, the IP network-connected devices configuration is physically distributed and at least partially replicated such that when a comparison of a status information with respect to at least one of the network-connected devices, the status information having a most recent timestamp associated therewith is relied upon.

摘要翻译： 公开了一种逻辑上集中的物理分布式互联网协议（IP）网络连接的设备配置。 该技术最初接收有关IP网络连接的设备配置的配置信息。 然后将配置信息传播到与IP网络连接的设备配置耦合的多个设备。 具有相关时间戳的IP网络连接设备配置的至少一部分然后存储在其上具有数据存储的多个设备中的任一个上。 这样做，IP网络连接的设备配置被物理地分布并且至少部分地复制，使得当状态信息相对于至少一个网络连接的设备进行比较时，状态信息具有最近的时间戳相关联 依靠它。

公开(公告)号：US20080189397A1

公开(公告)日：2008-08-07

申请号：US11701004

申请日：2007-02-01

申请人： Robert G. Atkinson ,  William T. Blank

发明人： Robert G. Atkinson ,  William T. Blank

IPC分类号： G06F15/173

CPC分类号： H04L41/0873 ,  H04L29/06 ,  H04L41/00 ,  H04L41/0816 ,  H04L41/0856

摘要： A logically centralized physically distributed Internet protocol (IP) network-connected devices configuration is disclosed. The technology initially receives configuration information regarding an IP network-connected devices configuration. The configuration information is then disseminated to a plurality of devices coupled with the IP network-connected devices configuration. At least a portion of the IP network-connected devices configuration with a related timestamp is then stored on any of the plurality of devices having a datastore thereon. In so doing, the IP network-connected devices configuration is physically distributed and at least partially replicated such that when a comparison of a status information with respect to at least one of the network-connected devices, the status information having a most recent timestamp associated therewith is relied upon.

摘要翻译： 公开了一种逻辑上集中的物理分布式互联网协议（IP）网络连接的设备配置。 该技术最初接收有关IP网络连接的设备配置的配置信息。 然后将配置信息传播到与IP网络连接的设备配置耦合的多个设备。 具有相关时间戳的IP网络连接设备配置的至少一部分然后存储在其上具有数据存储的多个设备中的任一个上。 这样做，IP网络连接的设备配置被物理地分布并且至少部分地复制，使得当状态信息相对于至少一个网络连接的设备进行比较时，状态信息具有最近的时间戳相关联 依靠它。

公开(公告)号：US5488694A

公开(公告)日：1996-01-30

申请号：US937639

申请日：1992-08-28

申请人： Mark P. McKee ,  John Zapisek ,  David M. Bulfer ,  John M. Long ,  John R. Nickolls ,  William T. Blank

发明人： Mark P. McKee ,  John Zapisek ,  David M. Bulfer ,  John M. Long ,  John R. Nickolls ,  William T. Blank

IPC分类号： G06F13/42 ,  G06F13/00 ,  G06F13/38

CPC分类号： G06F13/423

摘要： To effect a block data transfer between a plurality of physical I/O devices coupled through interfaces to an I/O channel ("IOC") bus, a source logical device is established by programmably assigning to each of the physical device interfaces a logical device identifier, a leaf identifier determining when the physical device participates relative to the first data transfer in the block data transfer, a burst count specifying the number of consecutive transfers for which the physical device is responsible when its interleave period arrives, and an interleave factor identifying how often the physical device participates in the block data transfer. A destination logical device is similarly established. The source and logical devices are then activated to accomplish a block transfer of data between them. To permit different I/O processors to operate independently in making I/O requests, requests from each I/O processor are communicated to an IOC controller over another bus, which need not be a high performance bus, and are serviced to construct header packets in a transaction buffer identifying IOC transactions, including source and destination logical devices. When each packet is finished, the responsible I/O processor puts a pointer into a transaction queue, which is a FIFO register. Each IOC transaction is initiated as its corresponding pointer is popped from the transaction queue. Apparatus embodiments are disclosed as well.

摘要翻译： 为了实现通过与I / O通道（“IOC”）总线的接口耦合的多个物理I / O设备之间的块数据传输，通过可编程地向每个物理设备接口分配逻辑设备来建立源逻辑设备 标识符，确定物理设备何时相对于块数据传输中的第一数据传输参与的叶标识符，指定物理设备在其交织周期到达时负责的连续传输次数的突发计数，以及交织因子识别 物理设备参与块数据传输的频率。 类似地建立目的地逻辑设备。 然后激活源和逻辑设备以在它们之间实现数据的块传输。 为了允许不同的I / O处理器在进行I / O请求时独立运行，来自每个I / O处理器的请求通过不需要是高性能总线的另一总线传送给IOC控制器，并且被服务以构建报头包 在事务缓冲区中标识IOC事务，包括源和目标逻辑设备。 当每个数据包完成后，负责的I / O处理器将一个指针放入事务队列，这是一个FIFO寄存器。 每个IOC事务被启动，因为它的相应指针从事务队列弹出。 还公开了装置实施例。

公开(公告)号：US5243699A

公开(公告)日：1993-09-07

申请号：US802944

申请日：1991-12-06

申请人： John R. Nickolls ,  Won S. Kim ,  John Zapisek ,  William T. Blank

发明人： John R. Nickolls ,  Won S. Kim ,  John Zapisek ,  William T. Blank

IPC分类号： G06F15/173 ,  G06F15/80

CPC分类号： G06F15/8007 ,  G06F15/17393

摘要： A massively parallel processor includes an array of processor elements (20), of PEs, and a multi-stage router interconnection network (30), which is used both for I/O communications and for PE to PE communications. The I/O system (10) for the massively parallel processor is based on a globally shared addressable I/O RAM buffer memory (50) that has address and data buses (52) to the I/O devices (80, 82) and other address and data buses (42) which are coupled to a router I/O element array (40). The router I/O element array is in turn coupled to the router ports (e.g. S2.sub.-- 0.sub.-- X0) of the second stage (430) of the router interconnection network. The router I/O array provides the corner turn conversion between the massive array of router lines (32) and the relatively few buses (52) to the I/O devices.

摘要翻译： 大规模并行处理器包括PE的处理器元件阵列（20）和用于I / O通信和用于PE至PE通信的多级路由器互连网络（30）。 用于大规模并行处理器的I / O系统（10）基于具有到I / O设备（80,82）的地址和数据总线（52）的全局共享的可寻址I / O RAM缓冲存储器（50） 耦合到路由器I / O元件阵列（40）的其它地址和数据总线（42）。 路由器I / O元件阵列又耦合到路由器互连网络的第二级（430）的路由器端口（例如，S2-0-X0）。 路由器I / O阵列提供大量路由器线路（32）和相对较少的总线（52）到I / O设备之间的拐角转换。

公开(公告)号：US4939642A

公开(公告)日：1990-07-03

申请号：US426539

申请日：1989-10-24

申请人： William T. Blank

发明人： William T. Blank

IPC分类号： G06F15/80

CPC分类号： G06F15/8023

摘要： A single instruction multiple data parallel processor has a rectangular array of processing elements which is smaller than the array of data to be processed. The array of data to be processed is divided into a number of segments, each equal in size to the processing element array. Each processing element includes a memory for storing one or more data values corresponding to one data element in each of these segments of the data array. To execute an instruction on all the data, the processing elements execute the instruction on one segment of the data array at a time, repeating the process until all the data has been processed. To do this, a primary address controller generates a sequence of segment address values for each instruction to be executed. The processing elements along the periphery of the processing element array are called edge processing elements. An edge address controller generates edge address values corresponding to the segment addresses of the segments neighboring the segment currently being addressed by the primary address controller. Each processing element is coupled to its neighbors so that it can execute instructions which require access to neighboring data elements. To enable edge processing elements to access neighboring data elements, each edge processing element has special hardware for accessing data values stored in a memory location corresponding to one of the edge address values.

摘要翻译： 单指令多数据并行处理器具有小于要处理的数据阵列的处理元件的矩形阵列。 要处理的数据阵列被划分成多个段，每个段的大小等于处理单元阵列。 每个处理元件包括存储器，用于存储对应于数据阵列的这些段的每一个中的一个数据元素的一个或多个数据值。 为了执行关于所有数据的指令，处理元件一次执行数据阵列的一个段上的指令，重复该过程，直到所有数据被处理。 为此，主地址控制器为要执行的每个指令生成一段段地址值。 沿处理元件阵列周边的处理元件称为边缘处理元件。 边缘地址控制器产生对应于与主地址控制器当前正在寻址的段相邻的段的段地址的边缘地址值。 每个处理元件耦合到其邻居，使得它可以执行需要访问相邻数据元素的指令。 为了使边缘处理元件能够访问相邻数据元素，每个边缘处理元件具有访问存储在对应于边缘地址值之一的存储器位置中的数据值的特殊硬件。