公开(公告)号：US5243699A

公开(公告)日：1993-09-07

申请号：US802944

申请日：1991-12-06

申请人： John R. Nickolls ,  Won S. Kim ,  John Zapisek ,  William T. Blank

发明人： John R. Nickolls ,  Won S. Kim ,  John Zapisek ,  William T. Blank

IPC分类号： G06F15/173 ,  G06F15/80

CPC分类号： G06F15/8007 ,  G06F15/17393

摘要： A massively parallel processor includes an array of processor elements (20), of PEs, and a multi-stage router interconnection network (30), which is used both for I/O communications and for PE to PE communications. The I/O system (10) for the massively parallel processor is based on a globally shared addressable I/O RAM buffer memory (50) that has address and data buses (52) to the I/O devices (80, 82) and other address and data buses (42) which are coupled to a router I/O element array (40). The router I/O element array is in turn coupled to the router ports (e.g. S2.sub.-- 0.sub.-- X0) of the second stage (430) of the router interconnection network. The router I/O array provides the corner turn conversion between the massive array of router lines (32) and the relatively few buses (52) to the I/O devices.

摘要翻译： 大规模并行处理器包括PE的处理器元件阵列（20）和用于I / O通信和用于PE至PE通信的多级路由器互连网络（30）。 用于大规模并行处理器的I / O系统（10）基于具有到I / O设备（80,82）的地址和数据总线（52）的全局共享的可寻址I / O RAM缓冲存储器（50） 耦合到路由器I / O元件阵列（40）的其它地址和数据总线（42）。 路由器I / O元件阵列又耦合到路由器互连网络的第二级（430）的路由器端口（例如，S2-0-X0）。 路由器I / O阵列提供大量路由器线路（32）和相对较少的总线（52）到I / O设备之间的拐角转换。

公开(公告)号：US5488694A

公开(公告)日：1996-01-30

申请号：US937639

申请日：1992-08-28

申请人： Mark P. McKee ,  John Zapisek ,  David M. Bulfer ,  John M. Long ,  John R. Nickolls ,  William T. Blank

发明人： Mark P. McKee ,  John Zapisek ,  David M. Bulfer ,  John M. Long ,  John R. Nickolls ,  William T. Blank

IPC分类号： G06F13/42 ,  G06F13/00 ,  G06F13/38

CPC分类号： G06F13/423

摘要： To effect a block data transfer between a plurality of physical I/O devices coupled through interfaces to an I/O channel ("IOC") bus, a source logical device is established by programmably assigning to each of the physical device interfaces a logical device identifier, a leaf identifier determining when the physical device participates relative to the first data transfer in the block data transfer, a burst count specifying the number of consecutive transfers for which the physical device is responsible when its interleave period arrives, and an interleave factor identifying how often the physical device participates in the block data transfer. A destination logical device is similarly established. The source and logical devices are then activated to accomplish a block transfer of data between them. To permit different I/O processors to operate independently in making I/O requests, requests from each I/O processor are communicated to an IOC controller over another bus, which need not be a high performance bus, and are serviced to construct header packets in a transaction buffer identifying IOC transactions, including source and destination logical devices. When each packet is finished, the responsible I/O processor puts a pointer into a transaction queue, which is a FIFO register. Each IOC transaction is initiated as its corresponding pointer is popped from the transaction queue. Apparatus embodiments are disclosed as well.

摘要翻译： 为了实现通过与I / O通道（“IOC”）总线的接口耦合的多个物理I / O设备之间的块数据传输，通过可编程地向每个物理设备接口分配逻辑设备来建立源逻辑设备 标识符，确定物理设备何时相对于块数据传输中的第一数据传输参与的叶标识符，指定物理设备在其交织周期到达时负责的连续传输次数的突发计数，以及交织因子识别 物理设备参与块数据传输的频率。 类似地建立目的地逻辑设备。 然后激活源和逻辑设备以在它们之间实现数据的块传输。 为了允许不同的I / O处理器在进行I / O请求时独立运行，来自每个I / O处理器的请求通过不需要是高性能总线的另一总线传送给IOC控制器，并且被服务以构建报头包 在事务缓冲区中标识IOC事务，包括源和目标逻辑设备。 当每个数据包完成后，负责的I / O处理器将一个指针放入事务队列，这是一个FIFO寄存器。 每个IOC事务被启动，因为它的相应指针从事务队列弹出。 还公开了装置实施例。

公开(公告)号：US5280474A

公开(公告)日：1994-01-18

申请号：US461492

申请日：1990-01-05

申请人： John R. Nickolls ,  John Zapisek ,  Won S. Kim ,  Jeffery C. Kalb ,  W. Thomas Blank ,  Eliot Wegbreit ,  Kevin Van Horn

发明人： John R. Nickolls ,  John Zapisek ,  Won S. Kim ,  Jeffery C. Kalb ,  W. Thomas Blank ,  Eliot Wegbreit ,  Kevin Van Horn

IPC分类号： G06F15/173 ,  G06F15/80 ,  H04L12/56

CPC分类号： G06F15/17393

摘要： A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.

摘要翻译： 公开了一种具有全局路由器网络的大规模并行计算机系统（500），其中流水线寄存器在空间上分布以增加全局路由器网络的消息传送速度。 全局路由器网络包括用于处理器到I / O（1700）消息传递的扩展抽头，以便I / O消息带宽与处理器间消息带宽相匹配。 路由开启消息分组包括与转向比特均匀对待的协议比特。 路由开启分组还包括冗余地址比特，用于向全球路由器网络内的路由器芯片赋予多交叉形状个性。 还公开了用于空间上支持大规模并行系统和全局路由器网络的处理器（700）的结构和方法。

公开(公告)号：US5598408A

公开(公告)日：1997-01-28

申请号：US182250

申请日：1994-01-14

申请人： John R. Nickolls ,  John Zapisek ,  Won S. Kim ,  Jeffrey C. Kalb ,  W. Thomas Blank ,  Eliot Wegbreit ,  Kevin Van Horn

发明人： John R. Nickolls ,  John Zapisek ,  Won S. Kim ,  Jeffrey C. Kalb ,  W. Thomas Blank ,  Eliot Wegbreit ,  Kevin Van Horn

IPC分类号： G06F15/173 ,  G06F15/80 ,  H04Q11/00

CPC分类号： G06F15/17393

摘要： A massively parallel computer system is disclosed having a global router network in which pipeline registers are spatially distributed to increase the messaging speed of the global router network. The global router network includes an expansion tap for processor to I/O messaging so that I/O messaging bandwidth matches interprocessor messaging bandwidth. A route-opening message packet includes protocol bits which are treated homogeneously with steering bits. The route-opening packet further includes redundant address bits for imparting a multiple-crossbars personality to router chips within the global router network. A structure and method for spatially supporting the processors of the massively parallel system and the global router network are also disclosed.

摘要翻译： 公开了一种具有全局路由器网络的大规模并行计算机系统，其中流水线寄存器在空间上分布以增加全局路由器网络的消息传送速度。 全局路由器网络包括用于处理器到I / O消息传递的扩展抽头，以便I / O消息带宽与处理器间消息带宽相匹配。 路由开启消息分组包括与转向比特均匀对待的协议比特。 路由开启分组还包括冗余地址比特，用于向全球路由器网络内的路由器芯片赋予多交叉形状个性。 还公开了用于空间支持大规模并行系统和全局路由器网络的处理器的结构和方法。

公开(公告)号：US5450330A

公开(公告)日：1995-09-12

申请号：US693850

申请日：1991-04-30

申请人： John Zapisek

发明人： John Zapisek

IPC分类号： G06F15/80 ,  G06F11/00 ,  G06F11/22 ,  G06F15/173 ,  G01R31/02

CPC分类号： G06F15/17393 ,  G06F11/22 ,  H04L49/101 ,  H04L49/555 ,  G06F11/1423

摘要： A router circuit for selectively connecting an input terminal of the router circuit to either a specified output terminal of the router circuit (crossbar personality) or to any of a group of output terminals of the router circuit associated with a single output channel (hyperbar personality). The router circuit is made configurable as either a crossbar switch or a hyperbar switch by dividing the router chip into sections, where each section is associated with a group of input terminals, and wherein various grant circuits within each of the sections have enable/disable input terminals connected by controllable switches to either enable/disable output terminals of grant circuits in an adjacent section (hyperbar personality) or to fixed logic levels (crossbar personality). In the crossbar configuration, for each input terminal of a section, only one grant circuit per channel is enabled. Each of the sections has a different set of grant circuits enabled per channel so that no two sections can access a same output terminal of the router chip. In the hyperbar configuration, the sections are made transparent, and grant circuits are enabled or disabled depending on output wire availability. Additionally, the router circuit contains novel routing address bit and protocol bit circuitry as well as novel diagnostic circuitry for detecting broken wires between router circuits.

摘要翻译： 一种路由器电路，用于选择性地将路由器电路的输入端连接到路由器电路的指定输出端（交叉开关人格）或与单个输出通道相关联的路由器电路的一组输出端（任意一个） 。 路由器电路通过将路由器芯片划分成各个部分而被配置为交叉开关或超级开关，其中每个部分与一组输入终端相关联，并且其中每个部分内的各种授权电路具有使能/禁止输入 通过可控开关连接的终端，以使能/禁用相邻部分（超级个性）中的授权电路的输出端或者固定逻辑电平（交叉开关人格）。 在横杆配置中，对于每个输入端子，每个通道只能启用一个授权电路。 每个部分具有每个通道启用的不同的授权电路集合，使得没有两个部分可以访问路由器芯片的相同的输出端子。 在超高速配置中，这些部分是透明的，并且根据输出线路可用性启用或禁用授权电路。 此外，路由器电路包含新颖的路由地址位和协议位电路，以及用于检测路由器电路之间的断线的新型诊断电路。

公开(公告)号：US5345556A

公开(公告)日：1994-09-06

申请号：US693846

申请日：1991-04-30

申请人： John Zapisek

发明人： John Zapisek

IPC分类号： G06F15/80 ,  G06F11/00 ,  G06F11/22 ,  G06F15/173 ,  G06F13/00

CPC分类号： G06F15/17393 ,  G06F11/22 ,  H04L49/101 ,  H04L49/555 ,  G06F11/1423

摘要： A router circuit for selectively connecting an input terminal of the router circuit to either a specified output terminal of the router circuit (crossbar personality) or to any of a group of output terminals of the router circuit associated with a single output channel (hyperbar personality). The router circuit is made configurable as either a crossbar switch or a hyperbar switch by dividing the router chip into sections, where each section is associated with a group of input terminals, and wherein various grant circuits within each of the sections have enable/disable input terminals connected by controllable switches to either enable/disable output terminals of grant circuits in an adjacent section (hyperbar personality) or to fixed logic levels (crossbar personality). In the crossbar configuration, for each input terminal of a section, only one grant circuit per channel is enabled. Each of the sections has a different set of grant circuits enabled per channel so that no two sections can access a same output terminal of the router chip. In the hyperbar configuration, the sections are made transparent, and grant circuits are enabled or disabled depending on output wire availability. Additionally, the router circuit contains novel routing address bit and protocol bit circuitry as well as novel diagnostic circuitry for detecting broken wires between router circuits.

摘要翻译： 一种路由器电路，用于选择性地将路由器电路的输入端连接到路由器电路的指定输出端（交叉开关人格）或与单个输出通道相关联的路由器电路的一组输出端（任意一个） 。 路由器电路可以通过将路由器芯片划分成各个部分而被配置为交叉开关或超级开关，其中每个部分与一组输入终端相关联，并且其中每个部分内的各种授权电路具有使能/禁止输入 通过可控开关连接的终端，以使能/禁用相邻部分（超级个性）中的授权电路的输出端或者固定逻辑电平（交叉开关人格）。 在横杆配置中，对于每个输入端子，每个通道只能启用一个授权电路。 每个部分具有每个通道启用的不同的授权电路集合，使得没有两个部分可以访问路由器芯片的相同的输出端子。 在超高速配置中，这些部分是透明的，并且根据输出线路可用性启用或禁用授权电路。 此外，路由器电路包含新颖的路由地址位和协议位电路，以及用于检测路由器电路之间的断线的新型诊断电路。

公开(公告)号：US5434977A

公开(公告)日：1995-07-18

申请号：US170657

申请日：1993-12-20

申请人： John Zapisek

发明人： John Zapisek

IPC分类号： G06F15/80 ,  G06F11/00 ,  G06F11/22 ,  G06F15/173 ,  G06F13/00

CPC分类号： G06F15/17393 ,  G06F11/22 ,  H04L49/101 ,  H04L49/555 ,  G06F11/1423

摘要： A router circuit for selectively connecting an input terminal of the router circuit to either a specified output terminal of the router circuit (crossbar personality) or to any of a group of output terminals of the router circuit associated with a single output channel (hyperbar personality). The router circuit is made configurable as either a crossbar switch or a hyperbar switch by dividing the router chip into sections, where each section is associated with a group of input terminals, and wherein various grant circuits within each of the sections have enable/disable input terminals connected by controllable switches to either enable/disable output terminals of grant circuits in an adjacent section (hyperbar personality) or to fixed logic levels (crossbar personality). In the crossbar configuration, for each input terminal of a section, only one grant circuit per channel is enabled. Each of the sections has a different set of grant circuits enabled per channel so that no two sections can access a same output terminal of the router chip. In the hyperbar configuration, the sections are made transparent, and grant circuits are enabled or disabled depending on output wire availability. Additionally, the router circuit contains novel routing address bit and protocol bit circuitry as well as novel diagnostic circuitry/or detecting broken wires between router circuits.

摘要翻译： 一种路由器电路，用于选择性地将路由器电路的输入端连接到路由器电路的指定输出端（交叉开关人格）或与单个输出通道相关联的路由器电路的一组输出端（任意一个） 。 路由器电路可以通过将路由器芯片划分成各个部分而被配置为交叉开关或超级开关，其中每个部分与一组输入终端相关联，并且其中每个部分内的各种授权电路具有使能/禁止输入 通过可控开关连接的终端，以使能/禁用相邻部分（超级个性）中的授权电路的输出端或者固定逻辑电平（交叉开关人格）。 在横杆配置中，对于每个输入端子，每个通道只能启用一个授权电路。 每个部分具有每个通道启用的不同的授权电路集合，使得没有两个部分可以访问路由器芯片的相同的输出端子。 在超高速配置中，这些部分是透明的，并且根据输出线路可用性启用或禁用授权电路。 此外，路由器电路包含新颖的路由地址位和协议位电路以及新的诊断电路/或检测路由器电路之间的断线。