公开(公告)号：US5508734A

公开(公告)日：1996-04-16

申请号：US281331

申请日：1994-07-27

申请人： Robert G. Baker ,  Kevin Kettler ,  Gustavo A. Suarez ,  Kenneth A. Uplinger ,  Candace J. F. Freedenberg

发明人： Robert G. Baker ,  Kevin Kettler ,  Gustavo A. Suarez ,  Kenneth A. Uplinger ,  Candace J. F. Freedenberg

IPC分类号： G03B15/00 ,  G02B3/00 ,  G02B6/04 ,  G02B6/06 ,  G02B13/04 ,  G02B13/06 ,  G02B13/16 ,  G03B19/00 ,  G06T1/00 ,  H04N5/225 ,  H04N5/232 ,  H04N5/262 ,  H04N7/14 ,  H04N7/15 ,  H04N7/18

CPC分类号： H04N7/142 ,  G02B13/06 ,  G02B3/0087 ,  G02B6/04 ,  G02B6/06 ,  H04N5/2628 ,  H04N7/15

摘要： A system for electronic imaging of a hemispheric field of view includes a camera for receiving optical images of the field of view and for producing output data corresponding to the optical images. The camera includes an optical assembly for producing images throughout a hemispheric field of view for optical conveyance to an imaging device or photographic film. The optical system assembly has lens components that selectively emphasize the peripheral content of the hemispheric field of view. An electronic imaging device within the camera or a film-to-digital date conversion system provides digitized output signals to input image memory or electronic storage devices. A transform processor selectively accesses and processes the digitized output signals from the input image memory according to user-defined criteria and stores the signals in output image memory. The signals in the output image memory can then be displayed according to the user-defined criteria.

摘要翻译： 用于半球视场的电子成像系统包括：摄像机，用于接收视野的光学图像，并产生对应于光学图像的输出数据。 相机包括用于在整个半球视野内产生图像以用于光学传输到成像装置或摄影胶片的光学组件。 光学系统组件具有选择性地强调半球视野的周边内容的透镜部件。 相机内的电子成像设备或电影数字日期转换系统向输入图像存储器或电子存储设备提供数字化的输出信号。 变换处理器根据用户定义的标准选择性地访问和处理来自输入图像存储器的数字化输出信号，并将该信号存储在输出图像存储器中。 然后可以根据用户定义的标准显示输出图像存储器中的信号。

公开(公告)号：US5450458A

公开(公告)日：1995-09-12

申请号：US286822

申请日：1994-08-05

申请人： Warren E. Price ,  Kenneth A. Uplinger

发明人： Warren E. Price ,  Kenneth A. Uplinger

IPC分类号： G06F1/12 ,  H04L7/00

CPC分类号： H04L7/0083 ,  G06F1/12

摘要： Data transfer between subsystems of an information handling system employing a multiple subsystem clock environment architecture, or between multiple information handling systems operating with different clock frequencies, is synchronized using a timing aligned multiple frequency synthesizer with a synchronization window decoder. A frequency generation circuit in circuit communication with a data synchronization circuit functions to produce a synchronized timing signal(s) to permit a central processing unit operating in one subsystem clock environment to function with a peripheral subsystem(s), such as a memory controller, operating in a different subsystem clock environment, or permits information handling systems operating with different clock frequencies to function with one another. Data transfer synchronization delays are reduced and mean-time-to-failure of signal synchronization accuracy is increased by eliminating metastability effects from the synchronization circuitry.

摘要翻译： 使用多子系统时钟环境架构的信息处理系统的子系统之间或者在使用不同的时钟频率工作的多个信息处理系统之间的数据传输与使用同步窗口解码器的定时对准的多频率合成器进行同步。 与数据同步电路进行电路通信的频率发生电路用于产生同步的定时信号，以允许在一个子系统时钟环境中操作的中央处理单元与外围子系统（诸如存储器控制器）一起工作， 操作在不同的子系统时钟环境中，或允许以不同时钟频率工作的信息处理系统彼此起作用。 通过消除来自同步电路的亚稳效应，减少数据传输同步延迟并增加信号同步精度的平均故障时间。

公开(公告)号：US5177747A

公开(公告)日：1993-01-05

申请号：US833563

申请日：1992-02-07

申请人： Louis B. Capps, Jr. ,  Jimmy G. Foster ,  Warren E. Price ,  Robert W. Rupe ,  Kenneth A. Uplinger

发明人： Louis B. Capps, Jr. ,  Jimmy G. Foster ,  Warren E. Price ,  Robert W. Rupe ,  Kenneth A. Uplinger

IPC分类号： G06F11/07 ,  G06F11/10

CPC分类号： G06F11/1044 ,  G06F11/073 ,  G06F11/0772

摘要： A personal computer has two memory banks respectively connected to two parity check units operative to detect parity errors. Upon doing so, each unit feeds a parity error signal to a separate latch. The latches are connected to a logic circuit which is in turn connected to an interrupt controller that initiates an interrupt when a parity error occurs. One latch is further connected to a check bit of a register of an I/O port and the check bit is set by the one latch. An interrupt handler reads the register and provides messages indicating which memory bank caused the parity error.

摘要翻译： 个人计算机具有分别连接到两个奇偶校验单元的两个存储体，用于检测奇偶校验错误。 在这样做时，每个单元将奇偶校验错误信号馈送到单独的锁存器。 锁存器连接到逻辑电路，逻辑电路又连接到当发生奇偶校验错误时启动中断的中断控制器。 一个锁存器进一步连接到I / O端口的寄存器的校验位，并且校验位由一个锁存器设置。 中断处理程序读取寄存器并提供指示哪个存储器组引起奇偶校验错误的消息。