公开(公告)号：US07568061B2

公开(公告)日：2009-07-28

申请号：US11463758

申请日：2006-08-10

申请人： Robert H. C. Lin ,  Prasenjit Roy ,  William B. Schwartz

发明人： Robert H. C. Lin ,  Prasenjit Roy ,  William B. Schwartz

IPC分类号： G06F13/00

CPC分类号： G06F13/385

摘要： Methods, apparatus, and products are disclosed for initializing expansion adapters installed in a computer system having similar expansion adapters that include detecting an expansion adapter installed in a computer system having a plurality of expansion adapters, the detected expansion adapter having an option ROM containing initialization code, identifying similar expansion adapters installed in the computer system that correspond to the detected expansion adapter, each of the identified similar expansion adapters having an option ROM containing initialization code, disabling the option ROM of each of the identified similar expansion adapters, and initializing the plurality of expansion adapters installed in the computer system without executing the initialization code of the identified similar expansion adapters.

摘要翻译： 公开了用于初始化安装在具有类似扩展适配器的计算机系统中的扩展适配器的方法，装置和产品，该扩展适配器包括检测安装在具有多个扩展适配器的计算机系统中的扩展适配器，检测到的扩展适配器具有包含初始化代码 识别安装在与所检测到的扩展适配器对应的计算机系统中的类似扩展适配器，每个识别的类似扩展适配器具有包含初始化代码的选项ROM，禁用每个所标识的类似扩展适配器的选项ROM，以及初始化多个 的扩展适配器安装在计算机系统中，而不执行所识别的类似扩展适配器的初始化代码。

公开(公告)号：US20080040525A1

公开(公告)日：2008-02-14

申请号：US11463758

申请日：2006-08-10

申请人： Robert H. C. Lin ,  Prasenjit Roy ,  William B. Schwartz

发明人： Robert H. C. Lin ,  Prasenjit Roy ,  William B. Schwartz

IPC分类号： G06F13/00

CPC分类号： G06F13/385

摘要： Methods, apparatus, and products are disclosed for initializing expansion adapters installed in a computer system having similar expansion adapters that include detecting an expansion adapter installed in a computer system having a plurality of expansion adapters, the detected expansion adapter having an option ROM containing initialization code, identifying similar expansion adapters installed in the computer system that correspond to the detected expansion adapter, each of the identified similar expansion adapters having an option ROM containing initialization code, disabling the option ROM of each of the identified similar expansion adapters, and initializing the plurality of expansion adapters installed in the computer system without executing the initialization code of the identified similar expansion adapters.

摘要翻译： 公开了用于初始化安装在具有类似扩展适配器的计算机系统中的扩展适配器的方法，装置和产品，该扩展适配器包括检测安装在具有多个扩展适配器的计算机系统中的扩展适配器，检测到的扩展适配器具有包含初始化代码 识别安装在与所检测到的扩展适配器对应的计算机系统中的类似扩展适配器，每个识别的类似扩展适配器具有包含初始化代码的选项ROM，禁用每个所标识的类似扩展适配器的选项ROM，以及初始化多个 的扩展适配器安装在计算机系统中，而不执行所识别的类似扩展适配器的初始化代码。

公开(公告)号：US07987438B2

公开(公告)日：2011-07-26

申请号：US12113469

申请日：2008-05-01

申请人： Robert H. C. Lin ,  Prasenjit Roy ,  William B. Schwartz

发明人： Robert H. C. Lin ,  Prasenjit Roy ,  William B. Schwartz

IPC分类号： G06F17/50 ,  G06F13/00

CPC分类号： G06F13/387

摘要： A design structure embodied in a machine readable storage medium for at designing, manufacturing, and/or testing a design is disclosed for initializing expansion adapters installed in a computer system having similar expansion adapters that include detecting an expansion adapter installed in a computer system having a plurality of expansion adapters, the detected expansion adapter having an option ROM containing initialization code, identifying similar expansion adapters installed in the computer system that correspond to the detected expansion adapter, each of the identified similar expansion adapters having an option ROM containing initialization code, disabling the option ROM of each of the identified similar expansion adapters, and initializing the plurality of expansion adapters installed in the computer system without executing the initialization code of the identified similar expansion adapters.

摘要翻译： 公开了一种体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构，用于初始化安装在具有类似扩展适配器的计算机系统中的扩展适配器，其包括检测安装在具有 多个扩展适配器，检测到的扩展适配器具有包含初始化代码的选项ROM，识别安装在与检测到的扩展适配器对应的计算机系统中的类似扩展适配器，每个识别的类似扩展适配器具有包含初始化代码的选项ROM，禁用 每个所识别的类似扩展适配器的选项ROM，以及初始化安装在计算机系统中的多个扩展适配器，而不执行所识别的类似扩展适配器的初始化代码。

公开(公告)号：US20080209096A1

公开(公告)日：2008-08-28

申请号：US12113469

申请日：2008-05-01

申请人： ROBERT H.C. LIN ,  Prasenjit Roy ,  William B. Schwartz

发明人： ROBERT H.C. LIN ,  Prasenjit Roy ,  William B. Schwartz

IPC分类号： G06F13/00

CPC分类号： G06F13/387

摘要： A design structure embodied in a machine readable storage medium for at designing, manufacturing, and/or testing a design is disclosed for initializing expansion adapters installed in a computer system having similar expansion adapters that include detecting an expansion adapter installed in a computer system having a plurality of expansion adapters, the detected expansion adapter having an option ROM containing initialization code, identifying similar expansion adapters installed in the computer system that correspond to the detected expansion adapter, each of the identified similar expansion adapters having an option ROM containing initialization code, disabling the option ROM of each of the identified similar expansion adapters, and initializing the plurality of expansion adapters installed in the computer system without executing the initialization code of the identified similar expansion adapters.

摘要翻译： 公开了一种体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构，用于初始化安装在具有类似扩展适配器的计算机系统中的扩展适配器，其包括检测安装在具有 多个扩展适配器，检测到的扩展适配器具有包含初始化代码的选项ROM，识别安装在与检测到的扩展适配器对应的计算机系统中的类似扩展适配器，每个识别的类似扩展适配器具有包含初始化代码的选项ROM，禁用 每个所识别的类似扩展适配器的选项ROM，以及初始化安装在计算机系统中的多个扩展适配器，而不执行所识别的类似扩展适配器的初始化代码。

公开(公告)号：US20090113197A1

公开(公告)日：2009-04-30

申请号：US11932849

申请日：2007-10-31

申请人： Sumeet Kochar ,  William B. Schwartz

发明人： Sumeet Kochar ,  William B. Schwartz

IPC分类号： G06F15/177

CPC分类号： G06F13/4068

摘要： A computer system that initializes a fraction of the computer system's memory for execution of video during booting of the computer system is provided. The computer system can include a first portion of BIOS code on a ROM device, wherein the first portion includes instructions for initializing the fraction. The computer system further can include a second portion of BIOS code that copies itself to the fraction upon completion of initialization of the fraction, wherein the second portion executes on the fraction and wherein the second portion initializes system memory and initializes a video buffer. The computer system further can include a copy of the second portion located on the ROM device, wherein the copy of the second portion executes until video buffer initialization is completed but before all of the system memory is initialized. Further, the video buffer displays video before all of the computer system's memory is initialized.

摘要翻译： 提供了一种在计算机系统引导期间初始化计算机系统的存储器的一部分用于执行视频的计算机系统。 计算机系统可以在ROM设备上包括BIOS代码的第一部分，其中第一部分包括用于初始化分数的指令。 计算机系统还可以包括第二部分BIOS代码，其在完成分数初始化时将其自身复制到分数，其中第二部分在分数上执行，其中第二部分初始化系统存储器并初始化视频缓冲器。 计算机系统还可以包括位于ROM设备上的第二部分的副本，其中第二部分的副本执行直到视频缓冲器初始化完成，但是在所有系统存储器被初始化之前。 此外，在所有计算机系统的存储器被初始化之前，视频缓冲器显示视频。

公开(公告)号：US07311548B1

公开(公告)日：2007-12-25

申请号：US11456494

申请日：2006-07-10

申请人： Scott N. Dunham ,  William B. Schwartz ,  Jeffrey B. Williams ,  Edward V. Zorek, Sr.

发明人： Scott N. Dunham ,  William B. Schwartz ,  Jeffrey B. Williams ,  Edward V. Zorek, Sr.

IPC分类号： H01R31/08

CPC分类号： H01R13/641 ,  H01R31/08

摘要： A jumper including a connecting face, a light-emitting face, and a light pipe extending from the connecting face to the light-emitting face is provided. The light pipe is operable to transmit a light from a provided computer hardware from the connecting face to the light-emitting face responsive to the jumper forming a circuit with the provided computer hardware. A method for fabricating a jumper is also provided. The method includes forming a plurality of receptacles on a connecting face of the jumper and incorporating a light pipe into the jumper such that the light pipe extends from the connecting face of the jumper to a light-emitting face of the jumper. A method for providing jumper installation feedback is further provided. The method includes mounting a jumper on a provided computer hardware and transmitting a light through the jumper responsive to the jumper forming a circuit with the provided computer hardware.

摘要翻译： 提供了包括连接面，发光面和从连接面向发光面延伸的光管的跳线。 光管可操作以将来自所提供的计算机硬件的光从连接面传送到发光面，以响应于跳线与所提供的计算机硬件形成电路。 还提供了制造跳线的方法。 该方法包括在跳线的连接面上形成多个插座并将光管并入到跳线中，使得光管从跳线的连接面延伸到跳线的发光面。 还提供了一种提供跳线安装反馈的方法。 该方法包括将跳线安装在所提供的计算机硬件上，并且响应于跳线与所提供的计算机硬件形成电路，通过跳线传输光。

公开(公告)号：US08793480B2

公开(公告)日：2014-07-29

申请号：US13443329

申请日：2012-04-10

申请人： Alfredo Aldereguia ,  Grace A. Richter ,  William B. Schwartz

发明人： Alfredo Aldereguia ,  Grace A. Richter ,  William B. Schwartz

IPC分类号： G06F15/177 ,  G06F21/57 ,  G06F9/00 ,  G06F9/44 ,  G06F1/24

CPC分类号： G06F15/177 ,  G06F1/24 ,  G06F8/65 ,  G06F9/00 ,  G06F9/4401 ,  G06F9/4406 ,  G06F21/572

摘要： Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.

摘要翻译： 在对称多处理（“SMP”）计算机中更新可编程逻辑器件（“PLD”），SMP计算机的每个计算节点包括耦合用于通过总线适配器进行数据通信的PLD，总线适配器适于通过一组 一个或多个输入/输出（'I / O'）存储器地址，包括使用PLD的配置指令的更新配置主计算节点; 在引导时，PLD在SMP引导中为每个计算节点上的每个总线适配器分配独特的一组一个或多个I / O地址; 并且在SMP引导期间由主计算节点向所有计算节点提供更新，通过每个总线适配器以唯一的单独的一个或多个I / O地址集合将更新作为数据传输写入到每个PLD 为每个总线适配器。

公开(公告)号：US08589672B2

公开(公告)日：2013-11-19

申请号：US12270888

申请日：2008-11-14

申请人： Shiva R. Dasari ,  Lee H. Wilson ,  Scott N. Durham ,  Sumeet Kochar ,  William B. Schwartz ,  Kenneth A. Goldman

发明人： Shiva R. Dasari ,  Lee H. Wilson ,  Scott N. Durham ,  Sumeet Kochar ,  William B. Schwartz ,  Kenneth A. Goldman

IPC分类号： H04L29/06 ,  H04L9/00 ,  G06F12/14 ,  G06F15/16

CPC分类号： G06F9/5061 ,  G06F21/57 ,  G06F2221/2105

摘要： Method, apparatus and computer program product are provided for operating a plurality of computer nodes while maintaining trust. A primary computer node and at least one secondary computer node are connected into a cluster, wherein each of the clustered computer nodes includes a trusted platform module (TPM) that is accessible to software and includes security status information about the respective computer node. Each clustered computer node is then merged into a single node with only the TPM of the primary computer node being accessible to software. The TPM of the primary computer node is updated to include the security status information of each TPM in the cluster. Preferably, the step of merging is controlled by power on self test (POST) basic input output system (BIOS) code associated with a boot processor in the primary node.

摘要翻译： 提供了用于操作多个计算机节点同时保持信任的方法，装置和计算机程序产品。 主计算机节点和至少一个辅助计算机节点连接到集群中，其中每个集群计算机节点包括可由软件访问的可信平台模块（TPM），并且包括关于相应计算机节点的安全状态信息。 然后将每个集群计算机节点合并到单个节点，只有主计算机节点的TPM才能被软件访问。 更新主计算机节点的TPM以包括集群中每个TPM的安全状态信息。 优选地，合并步骤由与主节点中的引导处理器相关联的上电自检（POST）基本输入输出系统（BIOS）代码来控制。

公开(公告)号：US20100325404A1

公开(公告)日：2010-12-23

申请号：US12486132

申请日：2009-06-17

申请人： Alfredo Aldereguia ,  Grace A. Richter ,  William B. Schwartz

发明人： Alfredo Aldereguia ,  Grace A. Richter ,  William B. Schwartz

IPC分类号： G06F15/177 ,  G06F13/14 ,  G06F12/00

CPC分类号： G06F15/177 ,  G06F1/24 ,  G06F8/65 ,  G06F9/00 ,  G06F9/4401 ,  G06F9/4406 ,  G06F21/572

摘要： Updating programmable logic devices (‘PLDs’) in a symmetric multiprocessing (‘SMP’) computer, each compute node of the SMP computer including a PLD coupled for data communications through a bus adapter, the bus adapter adapted for data communications through a set of one or more input/output (‘I/O’) memory addresses, including configuring the primary compute node with an update of the configuration instructions for the PLDs; assigning, by the PLDs at boot time in an SMP boot, a unique, separate set of one or more I/O addresses to each bus adapter on each compute node; and providing, by the primary compute node during the SMP boot, the update to all compute nodes, writing the update as a data transfer to each of the PLDs through each bus adapter at the unique, separate set of one or more I/O addresses for each bus adapter.

摘要翻译： 在对称多处理（“SMP”）计算机中更新可编程逻辑器件（“PLD”），SMP计算机的每个计算节点包括耦合用于通过总线适配器进行数据通信的PLD，总线适配器适于通过一组 一个或多个输入/输出（'I / O'）存储器地址，包括使用PLD的配置指令的更新配置主计算节点; 在引导时，PLD在SMP引导中为每个计算节点上的每个总线适配器分配独特的一组一个或多个I / O地址; 并且在SMP引导期间由主计算节点向所有计算节点提供更新，通过每个总线适配器以唯一的单独的一个或多个I / O地址集合将更新作为数据传输写入每个PLD 为每个总线适配器。

公开(公告)号：US07496708B2

公开(公告)日：2009-02-24

申请号：US11458477

申请日：2006-07-19

申请人： William E. Atherton ,  Richard A. Dayan ,  Scott N. Dunham ,  William B. Schwartz

发明人： William E. Atherton ,  Richard A. Dayan ,  Scott N. Dunham ,  William B. Schwartz

IPC分类号： G06F12/00

CPC分类号： G06F12/0623 ,  G06F9/4401 ,  G06F12/0223

摘要： Embodiments of the invention address deficiencies of the art in respect to boot ROM handling and provide a method, system and computer program product for optimized boot ROM handling for I/O devices. In one embodiment of the invention, a ROM scan area optimization method can be provided. The method can include pre-processing multiple boot ROM images to determine memory space requirements in the ROM scan area for all of the boot ROM images. The method further can include partitioning the ROM scan area into multiple, different static portions and at least one dynamic paged portion. Finally, the method can include generating an optimal arrangement of the boot ROM images defining placement of some of the boot ROM images in corresponding ones of the static portions, and others of the boot ROM images in the dynamic paged portion.

摘要翻译： 本发明的实施例解决了关于引导ROM处理的本领域的缺陷，并提供了用于I / O设备的优化引导ROM处理的方法，系统和计算机程序产品。 在本发明的一个实施例中，可以提供ROM扫描区域优化方法。 该方法可以包括预处理多个引导ROM映像，以确定所有引导ROM映像的ROM扫描区域中的存储器空间要求。 该方法还可以包括将ROM扫描区域划分成多个不同静态部分和至少一个动态分页部分。 最后，该方法可以包括生成引导ROM图像的最优布置，其将一些引导ROM图像的定位放置在动态分页部分中的静态部分和其他引导ROM图像中的相应静态部分中。