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公开(公告)号：US5198817A
公开(公告)日：1993-03-30
申请号：US514988
申请日：1990-04-26
IPC分类号： H03M3/04
摘要： A precision sigma-delta analog-to-digital converter disposed to operate at a sampling rate giving rise to a relatively low oversampling ratio is disclosed herein. The high-order sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal to a digital output sequence. The inventive converter (10) includes a first integrating network (14) for generating a first sampled analog signal (X.sub.1) in response to the analog input signal. A second integrating network (18) generates a second sampled analog signal (X.sub.2) in response to the first sampled analog signal (X.sub.1). A third integrating network (22) generates a third sampled analog signal (X.sub.3) in response to the second sampled analog signal (X.sub.2). The sigma-delta converter (10) of the present invention further includes an internal quantizer (24) for generating the digital output sequence in response to the third sampled analog signal. A feedback network (28, 30) supplies the first, second and integrating networks (14, 18 and 22) with an analog feedback signal generated in response to the digital output sequence.
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公开(公告)号：US5153593A
公开(公告)日：1992-10-06
申请号：US514990
申请日：1990-04-26
摘要： A precision sigma-delta A/D converter having a desired number of cascaded stages is disclosed herein. The multi-stage sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal X(z) to an output sequence of digital words. The converter (10) of the present invention includes a first sigma-delta converter stage (14) for generating a first sequence of digital words and a quantization error signal in response to the analog input signal X(z). An interstage amplifier (34) then amplifies the quantization error signal by a first gain factor G. The present invention further includes a second sigma-delta converter stage (18) for generating a second sequence of digital words in response to the amplified quantization error signal. The first and second sequences are next filtered by a digital noise cancellation network (31, 32) and the filtered second sequence is divided by the first gain factor G via a divider circuit (38). A summing circuit (40) provides the output sequence of digital words by summing the filtered first sequence and the divided second sequence. The digital noise cancellation network (32) is also used to compensate for errors due to analog component imperfections, e.g., capacitor mismatches and finite operational amplifier gain.
摘要翻译： 本文公开了具有期望数量的级联级的精度Σ-ΔA/ D转换器。 本发明的多级Σ-Δ模数转换器（10）可操作以将模拟输入信号X（z）转换为数字字的输出序列。 本发明的转换器（10）包括用于响应于模拟输入信号X（z）产生数字字的第一序列和量化误差信号的第一Σ-Δ转换器级（14）。 级间放大器（34）然后通过第一增益因子G放大量化误差信号。本发明还包括第二Σ-Δ转换器级（18），用于响应于放大的量化误差信号产生第二数字字序列 。 第一和第二序列接下来被数字噪声消除网络（31,32）滤波，并且滤波的第二序列经由除法电路（38）被第一增益因子G除。 求和电路（40）通过对经滤波的第一序列和分割的第二序列相加来提供数字字的输出序列。 数字噪声消除网络（32）还用于补偿由于模拟部件缺陷引起的误差，例如电容器失配和有限运算放大器增益。
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