-
公开(公告)号：US06380552B2
公开(公告)日：2002-04-30
申请号：US09322260
申请日：1999-05-28
申请人： Adele E. Schmitz , Robert H. Walden , Mark Lui , Mark K. Yu
发明人： Adele E. Schmitz , Robert H. Walden , Mark Lui , Mark K. Yu
IPC分类号： H01L2906
CPC分类号： H01L29/155 , H01L29/475 , H01L29/872
摘要： A Schottky diode, and a method of making the same, which is fabricated on InP material and employs a Schottky layer including InxAl1−xAs with x>0.6, or else including a chirped graded supperlattice in which successive periods of the superlattice contain progressively less GaInAs and progressively more AlInAs, the increase in AlInAs being terminated before the proportion of AlInAs within the last period (adjacent the anode metal) exceeds 80%. Such fabrication creates an InP-based Schottky diode having a low turn-on voltage which may be predictably set within a range by adjusting the fabrication parameters.
摘要翻译： 肖特基二极管及其制造方法，其制造在InP材料上，并采用包括x> 0.6的In x Al 1-x As的肖特基层，或者包括啁啾分级超晶格，其中超晶格的连续周期含有逐渐减少的GaInAs 并且逐渐增加AlInAs，AlInAs在上一期（邻近阳极金属）的比例超过80％之前终止的AlInAs的增加。 这种制造产生具有低导通电压的基于InP的肖特基二极管，其可以通过调整制造参数在一定范围内可预测地设置。
-
公开(公告)号：US5336624A
公开(公告)日：1994-08-09
申请号：US986637
申请日：1992-12-07
申请人： Robert H. Walden
发明人： Robert H. Walden
IPC分类号： H01L21/82 , H01L27/02 , H03K19/0944 , H03K19/0948 , H03K19/0952 , H01L21/265
CPC分类号： H01L27/02
摘要： Focussed ion beam (FIB) implants (38,40) are used to set the threshold voltages of metal-oxide-semiconductor field-effect transistors (MOSFETs) in a selected logic gate (34,36) in a microelectronic integrated digital logic circuit (31) such that the direct current (DC) transfer function and logic thresholds are essentially the same as for another logic gate (30,32) which is not altered by FIB implants, but the switching speed is greatly reduced. This causes the altered gate (34,36) to switch in an apparently normal manner when tested under DC or low speed conditions, but to not switch at normal operating speed. The altered or disguised gate (34,36) is thereby always on or always off at the normal operating speed, whereas the unaltered gate (30,32) switches in the normal manner. This impedes attempts at reverse engineering since the circuit (31) operates differently under test and operating conditions, and the true logic functions of the gate (34,36) cannot be determined by known low speed test procedures.
摘要翻译： 聚焦离子束（FIB）注入（38,40）用于在微电子集成数字逻辑电路（34,36）中的选定逻辑门（34,36）中设置金属氧化物半导体场效应晶体管（MOSFET）的阈值电压 31），使得直流（DC）传递函数和逻辑门限基本上与不被FIB种植体改变的另一逻辑门（30,32）相同，但是切换速度大大降低。 这导致改变的门（34,36）在直流或低速条件下测试时以明显正常的方式切换，但是在正常操作速度下不切换。 改变或伪装的门（34,36）因此在正常操作速度下始终处于或总是关闭，而未改变的门（30,32）以正常方式切换。 这阻碍了逆向工程的尝试，因为电路（31）在测试和操作条件下运行不同，并且门（34,36）的真实逻辑功能不能通过已知的低速测试程序来确定。
-
公开(公告)号：US4872010A
公开(公告)日：1989-10-03
申请号：US153750
申请日：1988-02-08
IPC分类号： H01L21/265 , H01L27/12 , H01L29/06 , H01L29/78 , H01L29/786 , H03M1/00 , H03M1/36
CPC分类号： H01L29/78696 , H01L27/12 , H01L29/0692 , H01L29/7838 , H01L29/78612 , H01L29/78657 , H03M1/361
摘要： An analog-to-digital converter 10 employs a series of comparators 12, 14, 16 and 18. Each comparator includes at least one inverter consisting of a CMOS transistor pair including a P-channel transistor 22 and N-channel transistor 24. The threshold levels of the transistors 22, 24 are modified using focused ion beam implantation techniques to provide the comparators with monotonically increasing transistion levels.
摘要翻译： 模拟 - 数字转换器10采用一系列比较器12,14,16和18.每个比较器包括至少一个由包括P沟道晶体管22和N沟道晶体管24的CMOS晶体管对组成的反相器。阈值 使用聚焦离子束注入技术来修改晶体管22,24的电平，以使比较器具有单调递增的电流电平。
-
公开(公告)号：US06316342B1
公开(公告)日：2001-11-13
申请号：US09640458
申请日：2000-08-15
申请人： Adele E. Schmitz , Robert H. Walden , Mark Lui , Mark K. Yu
发明人： Adele E. Schmitz , Robert H. Walden , Mark Lui , Mark K. Yu
IPC分类号： H01L2100
CPC分类号： H01L29/155 , H01L29/475 , H01L29/872
摘要： A Schottky diode, and a method of making the same, which is fabricated on InP material and employs a Schottky layer including InxAl1−xAS with x>0.6, or else including a chirped graded superlattice in which successive periods of the superlattice contain progressively less GaInAs and progressively more AlInAs, the increase in AlInAs being terminated before the proportion of AlInAs within the last period (adjacent the anode metal) exceeds 80%. Such fabrication creates an InP-based Schottky diode having a low turn-on voltage which may be predictably set within a range by adjusting the fabrication parameters
摘要翻译： 肖特基二极管及其制造方法，其制造在InP材料上并且采用包括x> 0.6的In x Al 1-xAS的肖特基层，或者包括啁啾分级超晶格，其中超晶格的连续周期包含逐渐减少的GaInAs 并且逐渐增加AlInAs，AlInAs在上一期（邻近阳极金属）的比例超过80％之前终止的AlInAs的增加。 这种制造产生了具有低导通电压的基于InP的肖特基二极管，其可以通过调整制造参数来预测地设置在一个范围内
-
公开(公告)号：US5198817A
公开(公告)日：1993-03-30
申请号：US514988
申请日：1990-04-26
IPC分类号： H03M3/04
摘要： A precision sigma-delta analog-to-digital converter disposed to operate at a sampling rate giving rise to a relatively low oversampling ratio is disclosed herein. The high-order sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal to a digital output sequence. The inventive converter (10) includes a first integrating network (14) for generating a first sampled analog signal (X.sub.1) in response to the analog input signal. A second integrating network (18) generates a second sampled analog signal (X.sub.2) in response to the first sampled analog signal (X.sub.1). A third integrating network (22) generates a third sampled analog signal (X.sub.3) in response to the second sampled analog signal (X.sub.2). The sigma-delta converter (10) of the present invention further includes an internal quantizer (24) for generating the digital output sequence in response to the third sampled analog signal. A feedback network (28, 30) supplies the first, second and integrating networks (14, 18 and 22) with an analog feedback signal generated in response to the digital output sequence.
-
公开(公告)号：US06525682B2
公开(公告)日：2003-02-25
申请号：US09848499
申请日：2001-05-03
申请人： Daniel Yap , Robert H. Walden
发明人： Daniel Yap , Robert H. Walden
IPC分类号： H03M112
摘要： A photonically sampled analog-to-digital converter using parallel channels of sampling and quantizing. The parallel combination achieves cancellation of the spurs that result from the nonlinear transfer function of the samplers. The samplers feed a dual-detector optoelectronic receiver that has differential inputs for suppression of laser intensity noise. The outputs of the multiple photonic samplers are averaged to reduce the effects of shot or thermal noise from the optoelectronic receiver of a sampler. The errors produced by the quantization process can be reduced by using a delta-sigma modulator-based analog-to-digital convertor as the quantizer which provides noise-spectrum shaping and filtering.
摘要翻译： 采用并行通道采样和量化的光子采样模数转换器。 并行组合实现了取样器的非线性传递函数所产生的杂散的消除。 采样器馈送双检测器光电接收器，其具有用于抑制激光强度噪声的差分输入。 对多个光子采样器的输出进行平均，以减少来自采样器的光电接收器的射击或热噪声的影响。 可以通过使用基于Δ-Σ调制器的模数转换器作为提供噪声谱整形和滤波的量化器来减少量化处理产生的误差。
-
7.发明授权
公开(公告)号：US5202591A
公开(公告)日：1993-04-13
申请号：US742799
申请日：1991-08-09
申请人： Robert H. Walden
发明人： Robert H. Walden
IPC分类号： H01L21/82 , H01L27/02 , H03K19/0944 , H03K19/0948 , H03K19/0952
CPC分类号： H01L27/02
摘要： Focussed ion beam (FIB) implants (38,40) are used to set the threshold voltages of metal-oxide-semiconductor field-effect transistors (MOSFETs) in a selected logic gate (34,36) in a microelectronic integrated digital logic circuit (31) such that the direct current (DC) transfer function and logic thresholds are essentially the same as for another logic gate (30,32) which is not altered by FIB implants, but the switching speed is greatly reduced. This causes the altered gate (34,36) to switch in an apparently normal manner when tested under DC or low speed conditions, but to not switch at normal operating speed. The altered or disguised gate (34,36) is thereby always on or always off at the normal operating speed, whereas the unaltered gate (30,32) switches in the normal manner. This impedes attempts at reverse engineering since the circuit (31) operates differently under test and operating conditions, and the true logic functions of the gate (34,36) cannot be determined by known low speed test procedures.
-
公开(公告)号：US4967250A
公开(公告)日：1990-10-30
申请号：US426481
申请日：1989-10-23
IPC分类号： H01L29/10
CPC分类号： H01L29/1062
摘要： A charge-coupled device (CCD) is provided with a dopant implant gradient, lateral channel stops and blocking implants by means of a focused ion beam (FIB). The FIB is repeatedly scanned across each cell of the CCD as a succession of overlapping but discrete implant scans. The doping levels of the FIB implants accumulate to a stepwise approximation of a desired dopant density profile, the widths of the steps being no greater than about half the widths of the discrete FIB implants. With a FIB pixel of about 750-1,500 Angstroms, the widths of the steps are preferably about 250-500 Angstroms; the dimension of the cells in the dopant gradient direction can be made less than about 5 microns. The lateral channel stops and back blocking implants can be as narrow as single FIB pixel widths, thus freeing up more of the cell for charge carrying capacity.
摘要翻译： 电荷耦合器件（CCD）具有掺杂剂注入梯度，侧向通道通过聚焦离子束（FIB）停止和阻塞植入物。 FIB被重复地扫描在CCD的每个单元上，作为一系列重叠但离散的植入物扫描。 FIB植入物的掺杂水平累积到期望掺杂剂密度分布的逐步近似，步长的宽度不大于离散FIB植入物的宽度的大约一半。 具有约750-1,500埃的FIB像素，步长的宽度优选为约250-500埃; 可以使掺杂剂梯度方向上的单元的尺寸小于约5微米。 横向通道停止，背部阻挡植入物可以与单个FIB像素宽度一样窄，从而释放出更多的电池用于充电容量。
-
公开(公告)号：US5153593A
公开(公告)日：1992-10-06
申请号：US514990
申请日：1990-04-26
摘要： A precision sigma-delta A/D converter having a desired number of cascaded stages is disclosed herein. The multi-stage sigma-delta analog-to-digital converter (10) of the present invention is operative to convert an analog input signal X(z) to an output sequence of digital words. The converter (10) of the present invention includes a first sigma-delta converter stage (14) for generating a first sequence of digital words and a quantization error signal in response to the analog input signal X(z). An interstage amplifier (34) then amplifies the quantization error signal by a first gain factor G. The present invention further includes a second sigma-delta converter stage (18) for generating a second sequence of digital words in response to the amplified quantization error signal. The first and second sequences are next filtered by a digital noise cancellation network (31, 32) and the filtered second sequence is divided by the first gain factor G via a divider circuit (38). A summing circuit (40) provides the output sequence of digital words by summing the filtered first sequence and the divided second sequence. The digital noise cancellation network (32) is also used to compensate for errors due to analog component imperfections, e.g., capacitor mismatches and finite operational amplifier gain.
摘要翻译： 本文公开了具有期望数量的级联级的精度Σ-ΔA/ D转换器。 本发明的多级Σ-Δ模数转换器（10）可操作以将模拟输入信号X（z）转换为数字字的输出序列。 本发明的转换器（10）包括用于响应于模拟输入信号X（z）产生数字字的第一序列和量化误差信号的第一Σ-Δ转换器级（14）。 级间放大器（34）然后通过第一增益因子G放大量化误差信号。本发明还包括第二Σ-Δ转换器级（18），用于响应于放大的量化误差信号产生第二数字字序列 。 第一和第二序列接下来被数字噪声消除网络（31,32）滤波，并且滤波的第二序列经由除法电路（38）被第一增益因子G除。 求和电路（40）通过对经滤波的第一序列和分割的第二序列相加来提供数字字的输出序列。 数字噪声消除网络（32）还用于补偿由于模拟部件缺陷引起的误差，例如电容器失配和有限运算放大器增益。
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.011 秒)