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公开(公告)号：US11863205B2
公开(公告)日：2024-01-02
申请号：US17538275
申请日：2021-11-30
Inventor： Abhishek Bandyopadhyay , Kaibo Miao , Langyuan Wang
CPC classification number: H03M3/464 , H03M1/183 , H03M3/354 , H03M3/424 , H03M3/452 , H03M3/456 , H03M3/458
Abstract: An apparatus comprises a sigma-delta analog-to-digital converter (ADC) circuit configured to convert an analog input signal to a digital value. The sigma-delta ADC circuit includes a loop filter circuit including at least one loop filter amplifier, a flash ADC circuit including multiple comparators, and a bias control circuit configured to change a biasing of the at least one loop filter amplifier according to outputs of the multiple comparators of the flash ADC circuit.
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2.发明授权Multi-bit delta-sigma time digitizer circuit and calibration method thereof 失效多位delta-sigma时间数字转换器电路及其校准方法公开(公告)号：US08779951B2
公开(公告)日：2014-07-15
申请号：US13767078
申请日：2013-02-14
Inventor： Satoshi Uemori , Masamichi Ishii , Haruo Kobayashi
CPC classification number: G04F10/005 , G01R25/00 , H03K5/26 , H03M3/354 , H03M3/424
Abstract: According to one embodiment, a multi-bit delta-sigma time digitizer circuit includes a delay array including delay selection circuits respectively including a delay element and a multiplexer, a phase comparator calculating a time difference, an integrator integrating the time difference output, a flash A/D converter executing digital conversion, a ring oscillation circuit including the delay array, a counter measuring a number of clock signal pulses, a memory storing a delay value of the delay element, and a processor correcting an output result of the A/D converter based on the delay value when the rising timing interval is measured.
Abstract translation: 根据一个实施例，多位delta-sigma时间数字转换器电路包括延迟阵列，包括分别包括延迟元件和复用器的延迟选择电路，计算时间差的相位比较器，积分时间差输出的积分器，闪光 执行数字转换的A / D转换器，包括延迟阵列的环形振荡电路，测量多个时钟信号脉冲的计数器，存储延迟元件的延迟值的存储器，以及校正A / D的输出结果的处理器 转换器基于在测量上升时间间隔时的延迟值。
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3.发明申请公开(公告)号：US20130214945A1
公开(公告)日：2013-08-22
申请号：US13767078
申请日：2013-02-14
Inventor： Satoshi UEMORI , Masamichi Ishii , Haruo Kobayashi
IPC: H03M3/00
CPC classification number: G04F10/005 , G01R25/00 , H03K5/26 , H03M3/354 , H03M3/424
Abstract: According to one embodiment, a multi-bit delta-sigma time digitizer circuit includes a delay array including delay selection circuits respectively including a delay element and a multiplexer, a phase comparator calculating a time difference, an integrator integrating the time difference output, a flash A/D converter executing digital conversion, a ring oscillation circuit including the delay array, a counter measuring a number of clock signal pulses, a memory storing a delay value of the delay element, and a processor correcting an output result of the A/D converter based on the delay value when the rising timing interval is measured.
Abstract translation: 根据一个实施例，多位delta-sigma时间数字转换器电路包括延迟阵列，包括分别包括延迟元件和复用器的延迟选择电路，计算时间差的相位比较器，积分时间差输出的积分器，闪光 执行数字转换的A / D转换器，包括延迟阵列的环形振荡电路，测量多个时钟信号脉冲的计数器，存储延迟元件的延迟值的存储器，以及校正A / D的输出结果的处理器 转换器基于在测量上升时间间隔时的延迟值。
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公开(公告)号：US07750837B2
公开(公告)日：2010-07-06
申请号：US12185046
申请日：2008-08-01
Applicant: Chuanyang Wang , Xiaohong Quan , Seyfollah Bazarjani
Inventor： Chuanyang Wang , Xiaohong Quan , Seyfollah Bazarjani
IPC: H03M1/12
CPC classification number: H03F1/303 , H03F3/005 , H03F3/195 , H03F3/45188 , H03F2200/357 , H03F2200/447 , H03F2200/451 , H03M3/354 , H03M3/392 , H03M3/43 , H03M3/454
Abstract: Techniques for adaptively generating bias current for a switched-capacitor circuit are described. The switched-capacitor circuit charges and discharges at least one switching capacitor at a sampling rate and may be a ΣΔ ADC that digitizes an analog signal at the sampling rate and provides digital samples. The switched-capacitor circuit may support multiple modes associated with different sampling rates. A bias circuit generates a bias current for the switched-capacitor circuit to be proportional to the sampling rate for a selected mode, to provide a bandwidth proportional to the sampling rate for an operational transconductance amplifier (OTA) within the switched-capacitor circuit, and to track changes in the switching capacitor(s) due to variations in integrated circuit (IC) process and temperature. The settling time of the switched-capacitor circuit may track with the multiple modes and across IC process and temperature variations.
Abstract translation: 描述用于自适应地产生开关电容器电路的偏置电流的技术。 开关电容电路以一个采样率对至少一个开关电容器进行充电和放电，并且可以是＆amp; ADC以采样率数字化模拟信号，并提供数字采样。 开关电容器电路可以支持与不同采样率相关联的多种模式。 偏置电路产生用于开关电容器电路的偏置电流与所选模式的采样率成比例，以提供与开关电容器电路内的工作跨导放大器（OTA）的采样率成比例的带宽，以及 以跟踪由于集成电路（IC）工艺和温度的变化而导致的开关电容器的变化。 开关电容器电路的稳定时间可以跟踪多种模式，并跨过IC工艺和温度变化。
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公开(公告)号：US20090002211A1
公开(公告)日：2009-01-01
申请号：US12097097
申请日：2006-12-11
Applicant: Lucien Johannes Breems , Dominicus Martinus Leenaerts
Inventor： Lucien Johannes Breems , Dominicus Martinus Leenaerts
IPC: H03M3/00
Abstract: A radio-frequency ΣΔ-modulator comprises a first mixer in the forward path for down-converting the signals in this forward path with a local oscillator frequency and a second mixer in the feedback path for up-converting the feedback signal with the same local oscillator frequency. Delays between the two mixing operations cause a loss of gain in the loop of the ΣΔ-modulator. An adjustable amplifier in the feedback path compensates for this loss of gain.
Abstract translation: 射频SigmaDelta调制器包括在正向路径中的第一混频器，用于以本地振荡器频率对该正向路径中的信号进行下变频，并且反馈路径中的第二混频器用于使用相同的本地振荡器对反馈信号进行上变频 频率。 两个混合操作之间的延迟导致SigmaDelta调制器的环路中的增益损失。 反馈路径中的可调放大器可补偿此增益损失。
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Patent Agency Ranking
公开(公告)号：US11777517B2
公开(公告)日：2023-10-03
申请号：US17096582
申请日：2020-11-12
Inventor： Chandra Prakash , Bhupendra Manola , John L. Melanson
IPC: H03M3/00
Abstract: An integrated circuit having multiple switched-capacitor delta-sigma data converter circuits includes compensation for voltage reference error due to leakage current that causes reference voltage droop. The reference filter capacitor terminal voltage is maintained by periodic connection to the reference feedback capacitor(s) that are alternately connected to a voltage reference buffer, and the leakage into the reference feedback capacitor networks of disabled converter circuits causes reference voltage droop. The compensation is either determined from the number of converter circuits that are disabled, or from an error between the filter capacitor voltage and a separate voltage reference, and may be applied by adjusting a resistance selectively coupled between the voltage reference buffer output and the filter capacitor, feedback applied to the voltage reference buffer or its input source. Alternatively, or in combination, correction may be applied to the output of the active converters by digital adjustment of output values.
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7.发明申请SIGNAL MODULATING DEVICE CAPABLE OF REDUCING PEAKING IN SIGNAL TRANSFER FUNCTION 有权信号调制装置，可减少信号传输功能中的峰值公开(公告)号：US20160056835A1
公开(公告)日：2016-02-25
申请号：US14600017
申请日：2015-01-20
Applicant: MEDIATEK INC.
Inventor： Li-Han Hung , Yen-Chuan Huang , Chi-Yun Wang , Chih-Hong Lou
IPC: H03M3/00
CPC classification number: H03M3/354 , H03H11/1252 , H03M3/404 , H03M3/438
Abstract: A signal modulating device includes: an integrating circuit arranged to generate an integrated signal according to a scaled analog signal and a first feedback signal; a resonating circuit arranged to generate a resonating signal according to the integrated signal; a first signal converting circuit arranged to convert the resonating signal into a digital output signal; a second signal converting circuit arranged to convert the digital output signal into the first feedback signal; and a first impedance circuit having a first terminal receiving an analog signal and a second terminal coupled to the resonating circuit for altering the location of zeros in the forward-path transfer function and consequently shaping the signal transfer function (STF) of the signal modulating device; and a second impedance circuit having a first terminal receiving the analog signal and a second terminal coupled to the integrating circuit for generating the scaled analog signal.
Abstract translation: 信号调制装置包括：积分电路，被配置为根据缩放的模拟信号和第一反馈信号产生积分信号; 谐振电路，被布置成根据积分信号产生谐振信号; 布置成将所述谐振信号转换为数字输出信号的第一信号转换电路; 布置成将数字输出信号转换成第一反馈信号的第二信号转换电路; 以及第一阻抗电路，其具有接收模拟信号的第一端子和耦合到所述谐振电路的第二端子，用于改变所述前向路径传递函数中的零点的位置，并因此整形所述信号调制装置的信号传递函数（STF） ; 以及第二阻抗电路，其具有接收模拟信号的第一端子和耦合到积分电路的第二端子，用于产生经缩放的模拟信号。
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公开(公告)号：US08847808B1
公开(公告)日：2014-09-30
申请号：US13913752
申请日：2013-06-10
Applicant: Broadcom Corporation
Inventor： Hongwu Chi , Michael Ming Lee
Abstract: A biasing circuit facilitates process, temperature, and voltage insensitive operation of a circuit block. The biasing circuit may include a replicate circuit corresponding to the circuit block. The replicate circuit may be a low complexity version of the circuit block that includes selected process, temperature, or voltage sensitive components of the circuit block. The biasing circuit enforces bias conditions on the circuit block that are informed by the response of the replicate circuit to variations in process, temperature, and voltage.
Abstract translation: 偏置电路有助于电路块的工艺，温度和电压不敏感操作。 偏置电路可以包括对应于电路块的复制电路。 复制电路可以是电路块的低复杂度版本，其包括电路块的所选择的处理，温度或电压敏感组件。 偏置电路对电路块施加偏压状态，该偏置状态由复制电路对过程，温度和电压变化的响应通知。
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9.发明授权公开(公告)号：US08519873B2
公开(公告)日：2013-08-27
申请号：US13229434
申请日：2011-09-09
Applicant: Venkatesh Srinivasan , Vijay B. Rentala , Victoria W. Limetkai , Baher Haroun
Inventor： Venkatesh Srinivasan , Vijay B. Rentala , Victoria W. Limetkai , Baher Haroun
IPC: H03M1/06
Abstract: In higher order sigma-delta modulators (SDMs), there are oftentimes errors introduced by the digital-to-analog (DAC) switches. Namely, parasitic capacitances associated with switches can introduce second harmonic spurs. Here, however, compensation circuits and buffers are provided. The buffers bias the switches in saturation, and the compensation circuits provide a “ground boost” for the buffers. The combination of the buffer and compensation circuit reduces the second harmonic spur, while also improving the Signal-to-Noise Ratio (SNR) and Signal-to-Noise-plus-Distortion Ratio (SNDR).
Abstract translation: 在高阶Σ-Δ调制器（SDM）中，通常由数模转换器（DAC）引入误差。 即，与开关相关的寄生电容可以引入二次谐波杂散。 然而，这里提供补偿电路和缓冲器。 缓冲器将开关偏置在饱和状态，补偿电路为缓冲器提供“接地提升”。 缓冲器和补偿电路的组合减少了二次谐波杂散，同时也提高了信噪比（SNR）和信噪比加失真比（SNDR）。
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公开(公告)号：US07605733B2
公开(公告)日：2009-10-20
申请号：US12097097
申请日：2006-12-11
IPC: H03M3/02
Abstract: A radio-frequency ΣΔ-modulator comprises a first mixer in the forward path for down-converting the signals in this forward path with a local oscillator frequency and a second mixer in the feedback path for up-converting the feedback signal with the same local oscillator frequency. Delays between the two mixing operations cause a loss of gain in the loop of the ΣΔ-modulator. An adjustable amplifier in the feedback path compensates for this loss of gain.
Abstract translation: 射频SigmaDelta调制器包括在正向路径中的第一混频器，用于以本地振荡器频率对该正向路径中的信号进行下变频，并且反馈路径中的第二混频器用于使用相同的本地振荡器对反馈信号进行上变频 频率。 两个混合操作之间的延迟导致SigmaDelta调制器的环路中的增益损失。 反馈路径中的可调放大器可补偿此增益损失。
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