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1.发明申请Apparatus And Method For Generating A Constant Logical Value In An Integrated Circuit 有权在集成电路中产生恒定逻辑值的装置和方法公开(公告)号：US20080204082A1
公开(公告)日：2008-08-28
申请号：US11677902
申请日：2007-02-22
IPC分类号： H03K19/0948
摘要： An apparatus for generating a constant logical value in an integrated circuit includes a first logic network having n outputs, the n outputs providing 2n possible output combinations, where the n outputs assume a state that is a subset of the 2n possible output combinations and a second logic network configured to generate at least one constant logic signal when the n outputs assume any state that is part of the subset of the 2n possible output combinations.
摘要翻译： 一种用于在集成电路中产生恒定逻辑值的装置包括具有n个输出的第一逻辑网络，所述n个输出提供2个可能的输出组合，其中n个输出采用作为 2 n可能的输出组合和第二逻辑网络，其被配置为当n个输出采用任何作为2个SUP的子集的一部分的状态时产生至少一个恒定逻辑信号 >可能的输出组合。
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2.发明授权Apparatus and method for generating a constant logical value in an integrated circuit 有权用于在集成电路中产生恒定逻辑值的装置和方法公开(公告)号：US07741879B2
公开(公告)日：2010-06-22
申请号：US11677902
申请日：2007-02-22
IPC分类号： H03K19/20
摘要： An apparatus for generating a constant logical value in an integrated circuit includes a first logic network having n outputs, the n outputs providing 2n possible output combinations, where the n outputs assume a state that is a subset of the 2n possible output combinations and a second logic network configured to generate at least one constant logic signal when the n outputs assume any state that is part of the subset of the 2n possible output combinations.
摘要翻译： 一种用于在集成电路中产生恒定逻辑值的装置包括具有n个输出的第一逻辑网络，所述n个输出提供2n个可能的输出组合，其中n个输出采取作为2n个可能的输出组合的子集的状态， 逻辑网络被配置为当n个输出采用任何作为2n个可能输出组合的子集的一部分的状态时产生至少一个恒定逻辑信号。
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3.发明申请公开(公告)号：US20050283698A1
公开(公告)日：2005-12-22
申请号：US10872793
申请日：2004-06-21
申请人： Gilbert Yoh , Manuel Salcido , Stan Perino
发明人： Gilbert Yoh , Manuel Salcido , Stan Perino
IPC分类号： G01R31/30 , G01R31/317 , G06F11/00
CPC分类号： G01R31/31725 , G01R31/3016
摘要： A simultaneous switching noise (SSN) test circuit and method are provided for measuring effects of SSN. Prior to testing for SSN, a signal is applied to the victim signal input pad and the rise and fall time delays associated with the victim signal are measured at the victim signal output pad. Then, one or more aggressor signals are simultaneously applied to respective input pads of one or more respective aggressor signal paths. The rise and fall time delays of the victim signal transmitted by the output pad are then measured and compared to the previously measured rise and fall time delays to determine effects of SSN on the victim signal caused by the aggressor signals.
摘要翻译： 提供同步开关噪声（SSN）测试电路和方法来测量SSN的影响。 在测试SSN之前，将一个信号施加到受害信号输入焊盘，并在受害信号输出焊盘处测量与受害信号相关联的上升和下降时间延迟。 然后，一个或多个侵略者信号同时施加到一个或多个相应侵略者信号路径的相应输入焊盘。 然后测量由输出焊盘发送的受害信号的上升和下降时间延迟，并将其与先前测量的上升和下降时间延迟进行比较，以确定SSN对侵扰者信号引起的受害信号的影响。
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4.发明授权Fixed termination scheme for differential receiver that compensates for process, voltage, and temperature variations 有权用于补偿过程，电压和温度变化的差分接收器的固定终端方案公开(公告)号：US06766155B2
公开(公告)日：2004-07-20
申请号：US10056164
申请日：2002-01-24
IPC分类号： H04B118
CPC分类号： H04L25/0272 , H04L25/0278 , H04L25/0292
摘要： A novel terminating differential bus receiver with automatic compensation for process, voltage, and temperature variation is presented. A termination circuit is connected internal to the integrated circuit to the input of a differential receiver in parallel with a transmission line connectable to the receiver. Both the termination circuit and the differential receiver are implemented with at least one p-channel transistor and at least one n-channel transistor, such that the p-channel transistors of the termination circuit and receiver and the n-channel transistors of the termination circuit and receiver are ratioed to vary similarly under PVT variation.
摘要翻译： 提出了一种具有自动补偿过程，电压和温度变化的新型终端差分总线接收器。 终端电路与集成电路的内部连接到差分接收器的输入并行连接到可接收器的传输线。 终端电路和差分接收器都由至少一个p沟道晶体管和至少一个n沟道晶体管实现，使得终端电路和接收器的p沟道晶体管和终端电路的n沟道晶体管 并且接收器的比例在PVT变化下变化相似。
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5.发明授权Stable process induced correction bias circuitry for receivers on single-ended applications 失效用于单端应用的接收器的稳定过程感应校正偏置电路公开(公告)号：US07313372B2
公开(公告)日：2007-12-25
申请号：US10902559
申请日：2004-07-29
申请人： Manuel Salcido , Gilbert Yoh , Guy Humphrey , Salvador Salcido
发明人： Manuel Salcido , Gilbert Yoh , Guy Humphrey , Salvador Salcido
CPC分类号： H04L25/0276 , H04L25/0296
摘要： A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.
摘要翻译： 第二单端接收机，具有用于接收输入信号并输出一对相应输出信号的第一级，以及用于接收一对输出信号并输出相应的单输出信号的第二级。 第一和第二下拉晶体管耦合到第一和第二输入到第一级。 偏置电路电偏置第一级，第二级以及第一和第二下拉式晶体管，并且电源为这些部件提供电力。
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6.发明授权公开(公告)号：US07159160B2
公开(公告)日：2007-01-02
申请号：US10872793
申请日：2004-06-21
申请人： Gilbert Yoh , Manuel Salcido , Stan Perino
发明人： Gilbert Yoh , Manuel Salcido , Stan Perino
CPC分类号： G01R31/31725 , G01R31/3016
摘要： A simultaneous switching noise (SSN) test circuit and method are provided for measuring effects of SSN. Prior to testing for SSN, a signal is applied to the victim signal input pad and the rise and fall time delays associated with the victim signal are measured at the victim signal output pad. Then, one or more aggressor signals are simultaneously applied to respective input pads of one or more respective aggressor signal paths. The rise and fall time delays of the victim signal transmitted by the output pad are then measured and compared to the previously measured rise and fall time delays to determine effects of SSN on the victim signal caused by the aggressor signals.
摘要翻译： 提供同步开关噪声（SSN）测试电路和方法来测量SSN的影响。 在测试SSN之前，将一个信号施加到受害信号输入焊盘，并在受害信号输出焊盘处测量与受害信号相关联的上升和下降时间延迟。 然后，一个或多个侵略者信号同时施加到一个或多个相应侵略者信号路径的相应输入焊盘。 然后测量由输出焊盘发送的受害信号的上升和下降时间延迟，并将其与先前测量的上升和下降时间延迟进行比较，以确定SSN对侵扰者信号引起的受害信号的影响。
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7.发明授权System and method for matching data and clock signal delays to improve setup and hold times 失效用于匹配数据和时钟信号延迟的系统和方法，以提高设置和保持时间公开(公告)号：US07194053B2
公开(公告)日：2007-03-20
申请号：US10046597
申请日：2001-12-18
申请人： Gilbert Yoh , Manuel Salcido , Scott T. Evans
发明人： Gilbert Yoh , Manuel Salcido , Scott T. Evans
CPC分类号： G06F1/10 , H04L7/0008
摘要： A system and method for providing a clock signal and data signal delay match to improve setup and hold times for integrated circuits is disclosed. In a simplified embodiment, the system comprises a clock receiver capable of removing noise from a received clock signal. A clock buffer is connected to the clock receiver and is capable of driving the received clock signal to a register. A data receiver is located within the system which is capable of removing noise from received data. In addition at least one miniature clock buffer is located within the system, wherein the at least one miniaturized clock buffer is a scaled version of the clock buffer having a scaling factor of K, the scaling factor representing a number of miniature clock buffers utilized to minimize negative variations experienced by the clock buffer.
摘要翻译： 公开了一种用于提供时钟信号和数据信号延迟匹配以提高集成电路的建立和保持时间的系统和方法。 在简化的实施例中，该系统包括能够从接收到的时钟信号中去除噪声的时钟接收器。 时钟缓冲器连接到时钟接收器，并且能够将接收到的时钟信号驱动到寄存器。 数据接收器位于系统内，能够从接收的数据中去除噪声。 此外，至少一个微型时钟缓冲器位于系统内，其中至少一个小型化时钟缓冲器是具有缩放因子K的时钟缓冲器的缩放版本，缩放因子表示用于最小化的微型时钟缓冲器的数量 时钟缓冲器经历的负面变化。
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8.发明申请Stable process induced correction bias circuitry for receivers on single-ended applications 失效用于单端应用的接收器的稳定过程感应校正偏置电路公开(公告)号：US20060025089A1
公开(公告)日：2006-02-02
申请号：US10902559
申请日：2004-07-29
申请人： Manuel Salcido , Gilbert Yoh , Guy Humphrey , Salvador Salcido
发明人： Manuel Salcido , Gilbert Yoh , Guy Humphrey , Salvador Salcido
IPC分类号： H04Q7/20
CPC分类号： H04L25/0276 , H04L25/0296
摘要： A second single-ended receiver having a first stage for receiving an input signal and outputting a pair of corresponding output signals, and a second stage for receiving the pair of output signals and outputting a corresponding single output signal. First and second pull-down transistors are coupled to first and second inputs to the first stage. A bias circuit electrically biases the first stage, second stage, and first and second pull-down transistors, and a power supply provides power to those components.
摘要翻译： 第二单端接收机，具有用于接收输入信号并输出一对相应输出信号的第一级，以及用于接收一对输出信号并输出相应的单输出信号的第二级。 第一和第二下拉晶体管耦合到第一和第二输入到第一级。 偏置电路电偏置第一级，第二级以及第一和第二下拉式晶体管，并且电源为这些部件提供电力。
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9.发明授权Internal bus termination technique for integrated circuits with local process/voltage/temperature compensation 有权具有局部过程/电压/温度补偿的集成电路的内部总线终端技术公开(公告)号：US06714039B2
公开(公告)日：2004-03-30
申请号：US10144112
申请日：2002-05-13
IPC分类号： H03K19003
CPC分类号： G06F13/4086
摘要： An active termination technique for reducing the propagation delay of a signal across a transmission line is presented. In accordance with a preferred embodiment of the invention, repeaters along a transmission line are paired with active termination circuits in very close proximity to the repeater in order to prevent signal reflections caused by the repeaters. The repeaters and associated active termination circuits are implemented with at least one PFET and at least one NFET, each having the same transistor gate lengths. The PFETs and the NFETs in the repeater and associated termination are ratioed to vary similarly over process/voltage/temperature variation.
摘要翻译： 提出了一种用于减少跨越传输线的信号的传播延迟的主动终止技术。 根据本发明的优选实施例，沿着传输线的中继器与非常接近中继器的有源终端电路配对，以便防止由中继器引起的信号反射。 中继器和相关的有源终端电路用至少一个PFET和至少一个NFET实现，每个NFET具有相同的晶体管栅极长度。 中继器和相关终端中的PFET和NFET的比值与过程/电压/温度变化相似。
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