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公开(公告)号：US20130111559A1
公开(公告)日：2013-05-02
申请号：US13286219
申请日：2011-11-01
申请人： Robert Lomme , Benjamin Wilde , Michael Tavis , Alexei Evdokimov , Siddharth R. Shah , Puneet Narula
发明人： Robert Lomme , Benjamin Wilde , Michael Tavis , Alexei Evdokimov , Siddharth R. Shah , Puneet Narula
CPC分类号： G06F17/30902 , G06F21/6245
摘要： A security trimming system disclosed herein uses intelligent caching of the security trimming information received from a security datastore. The security trimming system uses an access cache to store the security trimming information received from the access datastore together with other parameters associated with such security trimming information. Subsequently, in responding to a request for the security trimming information, the security trimming system uses the cached value of the security trimming information together with the other associated parameters to determine a response to the request from the content providers. In one implementation, if the other parameters associated with a particular security trimming information imply that the security trimming information in the cache is still valid, the cached security trimming information is used in the request response. Otherwise, a new request is sent to the security datastore for an updated value of the security trimming information.
摘要翻译： 本文公开的安全修整系统使用从安全数据存储区接收的安全修整信息的智能缓存。 安全修整系统使用访问高速缓存来存储从访问数据存储区接收的安全修整信息以及与这种安全修整信息相关联的其他参数。 随后，在响应对安全修整信息的请求时，安全修整系统使用安全修整信息的缓存值以及其他相关参数来确定来自内容提供者的对请求的响应。 在一个实现中，如果与特定安全性修整信息相关联的其他参数意味着高速缓存中的安全修整信息仍然有效，则在请求响应中使用缓存的安全修整信息。 否则，将向安全数据存储区发送新的请求以获取安全修整信息的更新值。
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公开(公告)号：US09336324B2
公开(公告)日：2016-05-10
申请号：US13286219
申请日：2011-11-01
申请人： Robert Lomme , Benjamin Wilde , Michael Tavis , Alexei Evdokimov , Siddharth R. Shah , Puneet Narula
发明人： Robert Lomme , Benjamin Wilde , Michael Tavis , Alexei Evdokimov , Siddharth R. Shah , Puneet Narula
CPC分类号： G06F17/30902 , G06F21/6245
摘要： A security trimming system disclosed herein uses intelligent caching of the security trimming information received from a security datastore. The security trimming system uses an access cache to store the security trimming information received from the access datastore together with other parameters associated with such security trimming information. Subsequently, in responding to a request for the security trimming information, the security trimming system uses the cached value of the security trimming information together with the other associated parameters to determine a response to the request from the content providers. In one implementation, if the other parameters associated with a particular security trimming information imply that the security trimming information in the cache is still valid, the cached security trimming information is used in the request response. Otherwise, a new request is sent to the security datastore for an updated value of the security trimming information.
摘要翻译： 本文公开的安全修整系统使用从安全数据存储区接收的安全修整信息的智能缓存。 安全修整系统使用访问高速缓存来存储从访问数据存储区接收的安全修整信息以及与这种安全修整信息相关联的其他参数。 随后，在响应对安全修整信息的请求时，安全修整系统使用安全修整信息的缓存值以及其他相关参数来确定来自内容提供者的对请求的响应。 在一个实现中，如果与特定安全性修整信息相关联的其他参数意味着高速缓存中的安全修整信息仍然有效，则在请求响应中使用缓存的安全修整信息。 否则，将向安全数据存储区发送新的请求以获取安全修整信息的更新值。
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公开(公告)号：US5590071A
公开(公告)日：1996-12-31
申请号：US559321
申请日：1995-11-16
摘要： A method and apparatus for emulating a high storage capacity DRAM component. The emulation involves the use of a component containing multiple DRAMs, each having a lower storage capacity than that of the emulated DRAM, but having a cumulative storage capacity greater than or equal to that of the DRAM being emulated. Emulation entails the decoding of extra bits in an address signal from a controller for the high capacity DRAM to direct the output of DRAM control signals from a decoder to the multiple DRAM component so as to activate only one of the plurality of lower density DRAMs therein. Advantageously, the invention may be implemented so as to permit migration to a next generation DRAM device without altering wiring on the printed circuit board or changing the memory controller used to access the DRAM component.
摘要翻译： 一种用于模拟高存储容量DRAM组件的方法和装置。 仿真涉及使用包含多个DRAM的部件，每个DRAM具有比仿真DRAM的存储容量更低的存储容量，但具有大于或等于被仿真的DRAM的累积存储容量。 仿真需要对来自用于高容量DRAM的控制器的地址信号中的额外位的解码，以将来自解码器的DRAM控制信号的输出引导到多个DRAM组件，以便仅激活其中的多个低密度DRAM中的一个。 有利地，本发明可以被实现为允许向下一代DRAM设备迁移，而不改变印刷电路板上的布线或改变用于访问DRAM组件的存储器控制器。
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公开(公告)号：US20110016471A1
公开(公告)日：2011-01-20
申请号：US12503147
申请日：2009-07-15
CPC分类号： G06F16/951
摘要： Balancing resource allocations based on priority may be provided. First, a plurality of repositories may be divided into at least two categories. Next, a first portion of computing resources may be dedicated to a first one of the at least two categories. Then a second portion of the computing resources may be dedicated to a second one of the at least two categories. A crawl may then be performed on the plurality of repositories with the computing resources.
摘要翻译： 可以提供基于优先级的资源分配平衡。 首先，多个存储库可以被划分为至少两个类别。 接下来，计算资源的第一部分可以专用于至少两个类别中的第一部分。 然后计算资源的第二部分可以专用于至少两个类别中的第二部分。 然后可以利用计算资源在多个存储库上执行爬行。
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5.发明授权Reconfigurable memory using both address permutation and spare memory elements 失效可重构存储器使用地址置换和备用存储器元件
公开(公告)号：US4584682A
公开(公告)日：1986-04-22
申请号：US528718
申请日：1983-09-02
摘要： An array substitution scheme is used to substitute a spare chip for a faulty chip when a UE condition results from an alignment of two errors in bit positions accessed through the same decoder while the bit permutation apparatus is used to misalign fault bits when they occur in bit positions accessed through different decoders.
摘要翻译： 当UE条件是通过同一解码器访问的比特位置中的两个错误的对齐产生的，而使用比特置换装置来使其发生位的错位时，将阵列替换方案替换为有缺陷的芯片的备用芯片 通过不同解码器访问的位置。
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