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公开(公告)号：US5053631A
公开(公告)日：1991-10-01
申请号：US503817
申请日：1990-04-02
申请人： Robert M. Perlman , Prem Sobel , Brian D. McMinn , Robert C. Thaden , Glenn A. Tamura , Thomas W. Lynch , Raju Vesgesna
发明人： Robert M. Perlman , Prem Sobel , Brian D. McMinn , Robert C. Thaden , Glenn A. Tamura , Thomas W. Lynch , Raju Vesgesna
CPC分类号： G06F7/483 , G06F2207/3884
摘要： A floating point processor for pipelining a series of calculations of simple and compound arithmetic operations includes at least one arithmetic operation unit for performing arithmetic operations on input operands provided to the arithmetic operation units and at least one accumulator for storing the results of the arithmetic operations performed by the arithmetic operation unit. The results stored in the accumulators are then provided to the arithmetic operation units. Arithmetic operations are pipelined through the floating point processor by a series of latches which sequence the input operands, results produced by the arithmetic operation units using the input operands, and results produced by the arithmetic operation units using the input operands and the accumulated operands.
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公开(公告)号：US5058048A
公开(公告)日：1991-10-15
申请号：US503819
申请日：1990-04-02
CPC分类号： G06F7/483 , G06F7/49936
摘要： A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When an denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent. If the result has a zero or negative exponent, the result is directed through the second arithmetic unit a second time so that the result is denormalized. The denormalized result is then output.
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公开(公告)号：US5267186A
公开(公告)日：1993-11-30
申请号：US734762
申请日：1991-07-23
CPC分类号： G06F7/483 , G06F7/49936
摘要： A floating point processor for performing arithmetic operations on floating point numbers includes a first arithmetic operation unit configured to operate on normalized numbers and a second arithmetic operation unit which includes a denormalizer for denormalizing normalized numbers and a normalizer for normalizing denormalized numbers. Each arithmetic operation unit has first and second inputs for receiving first and second operands, respectively, and an output for transmitting a result of the arithmetic operation. When a denormalized operand is presented as an input to the arithmetic operation unit configured to operate on normalized numbers, the denormalized input operand is redirected through the second arithmetic unit for normalization of the denormalized operand. The first arithmetic operation unit then performs its arithmetic operation using the normalized input operands. The result of the arithmetic operation is then analyzed to determine whether it has a zero or negative exponent. If the result has a zero or negative exponent, the result is directed through the second arithmetic unit a second time so that the result is denormalized. The denormalized result is then output.
摘要翻译： 用于对浮点数执行算术运算的浮点处理器包括：对归一化数进行运算的第一算术运算单元和包括用于对归一化数进行非归一化处理的非归一化器的第二算术运算单元和用于对非归一化数进行归一化的归一化器。 每个运算单元具有用于分别接收第一和第二操作数的第一和第二输入，以及用于发送算术运算结果的输出。 当将归一化操作数作为被配置为对归一化数进行操作的算术运算单元的输入进行表示时，通过第二算术单元重定向非正规化输入操作数，以对非归一化操作数进行归一化。 第一算术运算单元然后使用归一化的输入操作数进行算术运算。 然后分析算术运算的结果，以确定其是否具有零或负指数。 如果结果具有零或负指数，则结果第二次被引导通过第二运算单元，使得结果被非规范化。 然后输出非正规化结果。
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公开(公告)号：US20130014273A1
公开(公告)日：2013-01-10
申请号：US13619522
申请日：2012-09-14
申请人： Thomas W. Lynch
发明人： Thomas W. Lynch
IPC分类号： G06F21/00
CPC分类号： G06F21/577 , G06F21/606
摘要： Embodiments for validating protected data paths for digital rights management of digital objects are disclosed. Some embodiments disclosed herein may comprise processes or apparatus for transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, and/or further transfer and/or for transferring data from the computers or digital data processing systems to the peripherals. Some embodiments disclosed herein may comprise processes or apparatus for interconnecting or communicating between two or more components connected to an interconnection medium a within a single computer or digital data processing system.
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公开(公告)号：US20080228905A1
公开(公告)日：2008-09-18
申请号：US11685680
申请日：2007-03-13
申请人： Thomas W. Lynch
发明人： Thomas W. Lynch
IPC分类号： G06F15/173
CPC分类号： G06F1/263
摘要： One embodiment of a staging device comprises a power source capable of supplying power to a plurality of different portable devices, at least two portable devices having different power requirements. The power source comprises a fuel cell, a gel cell, a battery and/or a nuclear battery. Another embodiment of a staging device comprises a storage device capable of storing at least one of a message and data intended to be received by at least one of a plurality of portable devices, at least two portable devices having a different communication format. A controller coupled to the storage device is capable of converting the message and/or the data stored in the storage device to a communication format that is appropriate for an intended portable device.
摘要翻译： 分级设备的一个实施例包括能够向多个不同便携式设备供电的电源，至少两个具有不同功率要求的便携式设备。 电源包括燃料电池，凝胶电池，电池和/或核电池。 分级设备的另一实施例包括能够存储旨在由多个便携式设备中的至少一个接收的消息和数据中的至少一个的存储设备，至少两个具有不同通信格式的便携式设备。 耦合到存储设备的控制器能够将存储在存储设备中的消息和/或数据转换成适合于预期便携式设备的通信格式。
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公开(公告)号：US20080079716A1
公开(公告)日：2008-04-03
申请号：US11537532
申请日：2006-09-29
申请人： Thomas W. Lynch
发明人： Thomas W. Lynch
IPC分类号： G06T15/00
CPC分类号： G06T15/02
摘要： Embodiments of methods, devices and/or systems for modulating facial expressions to form a rendered face having an expression are described.
摘要翻译： 描述了用于调制面部表情以形成具有表情的呈现面部的方法，装置和/或系统的实施例。
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7.发明申请NETWORK RESOURCE ACCESS CONTROL METHODS AND SYSTEMS USING TRANSACTIONAL ARTIFACTS 审中-公开网络资源访问控制方法和使用交通工具的系统公开(公告)号：US20120317626A1
公开(公告)日：2012-12-13
申请号：US13592212
申请日：2012-08-22
申请人： Thomas W. Lynch
发明人： Thomas W. Lynch
CPC分类号： H04L63/08 , G06F21/31 , G06F2221/2101 , G06F2221/2129 , H04L63/10 , H04L2463/101
摘要： Methods and systems are provided for use with digital data processing systems to control or otherwise limit access to networked resources based, at least in part, on transactional artifacts and/or derived artifacts.
摘要翻译： 提供方法和系统用于数字数据处理系统以至少部分地基于事务性工件和/或衍生工件来控制或以其他方式限制对网络资源的访问。
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8.发明授权Protected intra-system interconnect for digital rights management in electrical computers and digital data processing systems 有权受保护的系统内互连，用于电子计算机和数字数据处理系统中的数字版权管理公开(公告)号：US08302200B2
公开(公告)日：2012-10-30
申请号：US11741493
申请日：2007-04-27
申请人： Thomas W. Lynch
发明人： Thomas W. Lynch
IPC分类号： G06F7/04
CPC分类号： H04L63/0428 , G06F21/10 , H04L2463/101
摘要： Embodiments including protected paths for digital rights management of digital objects are disclosed. Some embodiments disclosed herein may comprise processes or apparatus for transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, and/or further transfer and/or for transferring data from the computers or digital data processing systems to the peripherals. Some embodiments disclosed herein may comprise processes or apparatus for interconnecting or communicating between two or more components connected to an interconnection medium a within a single computer or digital data processing system.
摘要翻译： 公开了包括用于数字对象的数字权限管理的保护路径的实施例。 本文公开的一些实施例可以包括用于将数据从一个或多个外围设备传送到一个或多个计算机或数字数据处理系统的过程或装置，用于后者处理，存储和/或进一步传送和/或从计算机或/ 数字数据处理系统到外设。 本文公开的一些实施例可以包括用于在连接到单个计算机或数字数据处理系统内的互连介质a的两个或多个组件之间互连或通信的过程或装置。
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9.发明授权Validation of protected intra-system interconnects for digital rights management in electrical computers and digital data processing systems 有权验证电子计算机和数字数据处理系统中数字版权管理的受保护的系统内互连公开(公告)号：US08291501B2
公开(公告)日：2012-10-16
申请号：US12028669
申请日：2008-02-08
申请人： Thomas W. Lynch
发明人： Thomas W. Lynch
IPC分类号： G06F21/00
CPC分类号： G06F21/577 , G06F21/606
摘要： Embodiments for validating protected data paths for digital rights management of digital objects are disclosed. Some embodiments disclosed herein may comprise processes or apparatus for transferring data from one or more peripherals to one or more computers or digital data processing systems for the latter to process, store, and/or further transfer and/or for transferring data from the computers or digital data processing systems to the peripherals. Some embodiments disclosed herein may comprise processes or apparatus for interconnecting or communicating between two or more components connected to an interconnection medium within a single computer or digital data processing system.
摘要翻译： 公开了用于验证用于数字对象的数字版权管理的受保护数据路径的实施例。 本文公开的一些实施例可以包括用于将数据从一个或多个外围设备传送到一个或多个计算机或数字数据处理系统的过程或装置，用于后者处理，存储和/或进一步传送和/或从计算机或/ 数字数据处理系统到外设。 本文公开的一些实施例可以包括用于在连接到单个计算机或数字数据处理系统内的互连介质的两个或多个组件之间互连或通信的过程或装置。
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公开(公告)号：US08018722B2
公开(公告)日：2011-09-13
申请号：US12753739
申请日：2010-04-02
申请人： Thomas W. Lynch
发明人： Thomas W. Lynch
IPC分类号： H05K7/20
CPC分类号： H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： Embodiments described herein may include example embodiments of methods, apparatuses, devices, and/or systems for heat dissipation.
摘要翻译： 本文描述的实施例可以包括用于散热的方法，装置，装置和/或系统的示例实施例。
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