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公开(公告)号：US5740383A
公开(公告)日：1998-04-14
申请号：US577351
申请日：1995-12-22
CPC分类号： G06F13/18
摘要： An arbitration controller that temporarily raises the priority of a graphic device's HWM request above that of the BitBLT engine while that device's LWM request is being served. In this manner, the BitBLT engine cannot interrupt the transfer of data to the graphics device. Each device capable of issuing memory access requests is categorized into one of four classes. The LWM requests are the highest priority requests, followed by CPU memory access requests, then BitBLT engine requests, and finally by HWM requests. When a LWM request is granted, the requesting device's HWM request is elevated to a priority between the CPU and the BitBLT engine. Once the LWM request is complete, the HWM request is served until either it completes, the CPU issues a memory access request, or another LWM request occurs.
摘要翻译： 一个仲裁控制器，当该设备的LWM请求被提供时，临时提升图形设备的HWM请求的优先级高于BitBLT引擎的优先级。 以这种方式，BitBLT引擎不能中断数据传输到图形设备。 能够发出存储器访问请求的每个设备被分类为四个类中的一个。 LWM请求是最高优先级的请求，其次是CPU内存访问请求，然后是BitBLT引擎请求，最后是HWM请求。 当授予LWM请求时，请求设备的HWM请求被提升到CPU和BitBLT引擎之间的优先级。 一旦LWM请求完成，HWM请求就被提供，直到它完成，CPU发出内存访问请求，或者发生另一个LWM请求。
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2.发明授权Requesting device capable of canceling its memory access requests upon detecting other specific requesting devices simultaneously asserting access requests 失效请求设备能够在检测到其他特定请求设备同时断言访问请求时取消其存储器访问请求
公开(公告)号：US5748968A
公开(公告)日：1998-05-05
申请号：US583390
申请日：1996-01-05
CPC分类号： G09G5/001 , G06F13/18 , G09G2360/125 , G09G2360/128 , G09G5/363
摘要： A memory bandwidth allocation scheme in a computer system having a unified memory architecture. When a first device requesting access to a resource detects that two higher priority devices are also requesting access to the same resource, the first device shuts itself down. Accordingly, the first device deactivates its access request signals and clears its buffers. Then, the first device reactivates itself when it receives a graphics VSYNC signal. This allocation scheme ensures that the arbiter will not get stuck in a loop serving only high priority requests and not serving lower priority requests.
摘要翻译： 具有统一存储架构的计算机系统中的存储带宽分配方案。 当请求访问资源的第一设备检测到两个较高优先级的设备也请求访问同一资源时，第一设备自身关闭。 因此，第一设备停用其访问请求信号并清除其缓冲器。 然后，当第一个设备接收到图形VSYNC信号时，会自动重新启动。 该分配方案确保仲裁器不会卡在仅服务于高优先级请求而不服务较低优先级请求的循环中。
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公开(公告)号：US5862320A
公开(公告)日：1999-01-19
申请号：US577579
申请日：1995-12-22
CPC分类号： G06F11/2015
摘要： A keyboard controller is used to drive the PDEN pins on DIMMs. A PC has a keyboard controller with a plurality of programmable input/output (I/O) pins. The state of the programmable I/O pins can be set by software. The pins are coupled to individual PDEN pins on the DIMMs. When the programmable I/O pins are activated, the PDEN pins are driven active and each DIMM outputs a signal indicating its characteristics. The signals are latched and stored for use by a memory controller.
摘要翻译： 键盘控制器用于驱动DIMM上的PDEN引脚。 PC具有具有多个可编程输入/输出（I / O）引脚的键盘控制器。 可编程I / O引脚的状态可以通过软件进行设置。 引脚连接到DIMM上的各个PDEN引脚。 当可编程I / O引脚被激活时，PDEN引脚被激活，每个DIMM输出一个指示其特性的信号。 信号被锁存并存储以供存储器控制器使用。
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