公开(公告)号：US06215507B1

公开(公告)日：2001-04-10

申请号：US09089319

申请日：1998-06-01

申请人： Robert Marshall Nally ,  Pete Edward Nelsen

发明人： Robert Marshall Nally ,  Pete Edward Nelsen

IPC分类号： G06F1576

CPC分类号： G09G5/39 ,  G09G2340/125 ,  G09G2360/122 ,  G09G2360/123

摘要： Apparatus for generating and displaying data on a monitor 28 such as a CRT of LCD display. The display is comprised of a plurality of images, each located at positions on the face of the monitor defined by multi-digit coordinate values in a multi-coordinate system. Units of data are stored in linear display memory 26, each such unit of data corresponding to and defining the image to be displayed at one of said positions. The apparatus includes a circuit 60 which places selected bits of said multi-digit coordinate values in a preselected order to define the address or offset in said linear display memory at which is located the corresponding unit of data.

摘要翻译： 用于在诸如LCD显示器的CRT的监视器28上生成和显示数据的装置。 显示器包括多个图像，每个图像位于多坐标系中由多位数坐标值定义的监视器的表面上的位置处。 数据单元存储在线性显示存储器26中，每个这样的数据单元对应于并定义要在所述位置之一处显示的图像。 该装置包括电路60，其以预选的顺序放置所述多位数坐标值的选定位，以定义所述线性显示存储器中位于相应的数据单元的地址或偏移量。

公开(公告)号：US5748968A

公开(公告)日：1998-05-05

申请号：US583390

申请日：1996-01-05

申请人： Robert Marshall Nally ,  Pete Edward Nelsen ,  Douglas Hamilton ,  Douglas Michael Berk

发明人： Robert Marshall Nally ,  Pete Edward Nelsen ,  Douglas Hamilton ,  Douglas Michael Berk

IPC分类号： G06F13/18 ,  G09G1/16 ,  G09G5/00 ,  G09G5/36 ,  G06F13/36

CPC分类号： G09G5/001 ,  G06F13/18 ,  G09G2360/125 ,  G09G2360/128 ,  G09G5/363

摘要： A memory bandwidth allocation scheme in a computer system having a unified memory architecture. When a first device requesting access to a resource detects that two higher priority devices are also requesting access to the same resource, the first device shuts itself down. Accordingly, the first device deactivates its access request signals and clears its buffers. Then, the first device reactivates itself when it receives a graphics VSYNC signal. This allocation scheme ensures that the arbiter will not get stuck in a loop serving only high priority requests and not serving lower priority requests.

摘要翻译： 具有统一存储架构的计算机系统中的存储带宽分配方案。 当请求访问资源的第一设备检测到两个较高优先级的设备也请求访问同一资源时，第一设备自身关闭。 因此，第一设备停用其访问请求信号并清除其缓冲器。 然后，当第一个设备接收到图形VSYNC信号时，会自动重新启动。 该分配方案确保仲裁器不会卡在仅服务于高优先级请求而不服务较低优先级请求的循环中。

公开(公告)号：US5862320A

公开(公告)日：1999-01-19

申请号：US577579

申请日：1995-12-22

申请人： Pete Edward Nelsen ,  Douglas Michael Berk ,  Kenneth Ma

发明人： Pete Edward Nelsen ,  Douglas Michael Berk ,  Kenneth Ma

IPC分类号： G06F11/20 ,  G06F11/00

CPC分类号： G06F11/2015

摘要： A keyboard controller is used to drive the PDEN pins on DIMMs. A PC has a keyboard controller with a plurality of programmable input/output (I/O) pins. The state of the programmable I/O pins can be set by software. The pins are coupled to individual PDEN pins on the DIMMs. When the programmable I/O pins are activated, the PDEN pins are driven active and each DIMM outputs a signal indicating its characteristics. The signals are latched and stored for use by a memory controller.

摘要翻译： 键盘控制器用于驱动DIMM上的PDEN引脚。 PC具有具有多个可编程输入/输出（I / O）引脚的键盘控制器。 可编程I / O引脚的状态可以通过软件进行设置。 引脚连接到DIMM上的各个PDEN引脚。 当可编程I / O引脚被激活时，PDEN引脚被激活，每个DIMM输出一个指示其特性的信号。 信号被锁存并存储以供存储器控制器使用。

公开(公告)号：US5802581A

公开(公告)日：1998-09-01

申请号：US577584

申请日：1995-12-22

申请人： Pete Edward Nelsen

发明人： Pete Edward Nelsen

IPC分类号： G06F13/18

CPC分类号： G06F13/18

摘要： A computer system having a unified memory architecture (UMA) with a central SDRAM memory can be accessed by multiple devices. Arbitration logic receives and arbitrates among the memory requests. The memory controller indicates when the arbitration logic may issue a grant. The memory controller has two arbitration points during a memory cycle, an early one and a late one. A central processing unit (CPU), or other device, that misses the early arbitration point can still get memory access during the memory cycle by submitting a memory request before the late arbitration point.

摘要翻译： 具有中央SDRAM存储器的具有统一存储器架构（UMA）的计算机系统可被多个设备访问。 仲裁逻辑在存储器请求之间接收和仲裁。 存储器控制器指示仲裁逻辑何时可以发放授权。 存储器控制器在存储器循环期间具有两个仲裁点，即早期和晚期。 错过早期仲裁点的中央处理单元（CPU）或其他设备仍然可以通过在晚期仲裁点之前提交存储器请求在存储器周期内获得存储器访问。

公开(公告)号：US5802597A

公开(公告)日：1998-09-01

申请号：US579068

申请日：1995-12-22

申请人： Pete Edward Nelsen

发明人： Pete Edward Nelsen

IPC分类号： G06F13/16 ,  G06F12/04

CPC分类号： G06F13/161

摘要： An SDRAM memory controller that provides both burst four and single data transfers while keeping the SDRAM in burst four mode. A memory controller uses a DQMB�7:0! signal and a precharge command to stop the transference of data on the data bus during the time that the last 3 data elements would have been transferred. Specifically, during a single read, DQMB�7:0! is set high for two clock cycles causing the data bus to float during the time that the second and third data elements would have been on the bus. During a single write, DQMB�7:0! is set high for two clock cycles thereby preventing the second and third data elements from being written to memory. During a read, the precharge command causes the bus to float during the time the fourth element would have been on the bus. During a write, the precharge command prevents the fourth data element from being written.

摘要翻译： 一个SDRAM存储器控制器，提供突发四个和单个数据传输，同时保持SDRAM在突发四模式。 存储器控制器使用DQMB [7：0]信号和预充电命令在最后3个数据元素被传输的时间内停止数据总线上的数据传输。 具体来说，在单次读取期间，DQMB [7：0]在两个时钟周期内设置为高电平，导致数据总线在第二个和第三个数据元素将在总线上的时间内浮动。 在单次写入期间，DQMB [7：0]设置为两个时钟周期的高电平，从而防止第二和第三个数据元素写入存储器。 在读取期间，预充电命令使总线在第四个元件将在总线上的时间内浮动。 在写入期间，预充电命令防止第四数据元素被写入。

公开(公告)号：US5740383A

公开(公告)日：1998-04-14

申请号：US577351

申请日：1995-12-22

申请人： Robert Marshall Nally ,  Pete Edward Nelsen ,  Douglas Hamilton ,  Douglas Michael Berk

发明人： Robert Marshall Nally ,  Pete Edward Nelsen ,  Douglas Hamilton ,  Douglas Michael Berk

IPC分类号： G06F13/18 ,  G06F13/00

CPC分类号： G06F13/18

摘要： An arbitration controller that temporarily raises the priority of a graphic device's HWM request above that of the BitBLT engine while that device's LWM request is being served. In this manner, the BitBLT engine cannot interrupt the transfer of data to the graphics device. Each device capable of issuing memory access requests is categorized into one of four classes. The LWM requests are the highest priority requests, followed by CPU memory access requests, then BitBLT engine requests, and finally by HWM requests. When a LWM request is granted, the requesting device's HWM request is elevated to a priority between the CPU and the BitBLT engine. Once the LWM request is complete, the HWM request is served until either it completes, the CPU issues a memory access request, or another LWM request occurs.

摘要翻译： 一个仲裁控制器，当该设备的LWM请求被提供时，临时提升图形设备的HWM请求的优先级高于BitBLT引擎的优先级。 以这种方式，BitBLT引擎不能中断数据传输到图形设备。 能够发出存储器访问请求的每个设备被分类为四个类中的一个。 LWM请求是最高优先级的请求，其次是CPU内存访问请求，然后是BitBLT引擎请求，最后是HWM请求。 当授予LWM请求时，请求设备的HWM请求被提升到CPU和BitBLT引擎之间的优先级。 一旦LWM请求完成，HWM请求就被提供，直到它完成，CPU发出内存访问请求，或者发生另一个LWM请求。