公开(公告)号：US5526662A

公开(公告)日：1996-06-18

申请号：US174873

申请日：1993-12-28

申请人： Robert R. Diekhoff ,  Joseph H. Sutton ,  Hazem Hassan ,  Michael Boehner

发明人： Robert R. Diekhoff ,  Joseph H. Sutton ,  Hazem Hassan ,  Michael Boehner

IPC分类号： G06K19/04 ,  E05B49/00

CPC分类号： G06K19/04 ,  Y10T70/7062 ,  Y10T70/7073 ,  Y10T70/7881 ,  Y10T70/7904

摘要： A combination key-like device and electrical receptacle for the key-like device wherein the receptacle defines electrical contact surface areas for mating with corresponding contact surface areas defined by the key-like device. At least one clip defines the electrical contact surface areas for the said receptacle and the clip is supported on the receptacle body. A keyway opening is defined by the body and the clip comprises a transverse portion and a pair of legs extending outwardly from the transverse portion with contact elements defined by each of the legs extending inwardly toward the keyway opening and with openings defined by the body communicating with said keyway opening for receiving the contact elements. A contact band is carried by the key-like device whereby insertion of the key-like device into the keyway opening brings the contact band into electrical contact with at least one of the contact elements.

摘要翻译： 用于钥匙状装置的组合键状装置和电插座，其中插座限定用于与由键状装置限定的相应接触表面区域配合的电接触表面区域。 至少一个夹具限定用于所述插座的电接触表面区域，并且夹子支撑在插座主体上。 键体开口由主体限定，并且夹子包括从横向部分向外延伸的横向部分和一对腿部，其中每个腿部限定的接触元件朝向键槽开口向内延伸，并且具有与主体连通的开口 所述键槽开口用于接收接触元件。 接触带由键状装置承载，由此将键状装置插入键槽开口使接触带与至少一个接触元件电接触。

公开(公告)号：US4715035A

公开(公告)日：1987-12-22

申请号：US852661

申请日：1986-04-16

申请人： Michael Boehner

发明人： Michael Boehner

IPC分类号： G06F11/25 ,  G06F11/26 ,  G06F17/50 ,  G06F11/22 ,  G01R31/28

CPC分类号： G06F11/261

摘要： A method for the simulation of an error in a logic circuit which comprises a bus optionally connectible to different logic levels, utilizes the assistance of input bit patterns from which output bit patterns are derived via a simulation model containing the error, these output bit patterns being compared to reference bit patterns which are valid for error-free operation. The object is a reliable recognition of an error which leads to a bus conflict, by applying different logic levels to the same circuit mode, by way of an output bit pattern which deviates from a reference bit pattern. This is achieved in that the bus, including the switch elements connecting the levels, is modeled by gate functions, whereby the undefined bus level given simultaneous connection of different logical levels is imaged into a logical "0" by a first bus model version and is imaged into a "1" by a second bus model version. Both bus model versions are respectively utilized in one segment of the simulation method.

摘要翻译： 用于模拟包括可选地连接到不同逻辑电平的总线的逻辑电路中的错误的方法利用输入位模式的帮助，通过包含误差的仿真模型从其输出输出位模式，这些输出位模式为 与无差错操作有效的参考位模式进行比较。 该目的是通过将偏离参考位模式的输出位模式应用于相同电路模式的不同逻辑电平，导致总线冲突的错误的可靠识别。 这是因为包括连接电平的开关元件的总线由门功能建模，由此给予不同逻辑电平的同时连接的未定义总线电平通过第一总线模型版本成像为逻辑“0”，并且是 通过第二总线模型版本成像为“1”。 两种总线模型版本分别用于仿真方法的一个部分。