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公开(公告)号：US07127564B2
公开(公告)日：2006-10-24
申请号：US10376838
申请日：2003-02-28
申请人： Robert W. Schoepflin , Richard E. Wahler , Ronald W. Streiber , John D. Virzi , Donald D. Noviello
发明人： Robert W. Schoepflin , Richard E. Wahler , Ronald W. Streiber , John D. Virzi , Donald D. Noviello
IPC分类号： G06F12/02
CPC分类号： G06F12/0607 , G06F12/0246
摘要： A double buffered flash bank. In one embodiment, a flash interface may be programmed by a register interface with a first set of data while a second set of data is being written to the register interface. In one embodiment, flash banks may be programmed in parallel using latched register interfaces. For example, while data from a first register interface is being written to the first flash bank and data from a second register interface is being written to a second flash bank, new data may be written to the first register interface and to the second register interface. The new data may then be written from the first register interface to the first flash bank and from the second register interface to the second flash bank.
摘要翻译： 双缓冲闪存库。 在一个实施例中，闪存接口可以由具有第一组数据的寄存器接口编程，而第二组数据正被写入寄存器接口。 在一个实施例中，闪存组可以使用锁存寄存器接口并行编程。 例如，当来自第一寄存器接口的数据正被写入第一闪存组并且来自第二寄存器接口的数据正被写入第二闪存组时，新数据可被写入到第一寄存器接口和第二寄存器接口 。 然后可以将新数据从第一寄存器接口写入第一闪存组，并从第二寄存器接口写入第二闪存组。
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2.发明授权Switchable hot-docking interface for a portable computer for hot-docking the portable computer to a docking station 有权用于便携式计算机的可切换热插接口，用于将便携式计算机热插入对接站公开(公告)号：US06868468B2
公开(公告)日：2005-03-15
申请号：US10076105
申请日：2002-02-14
CPC分类号： G06F13/4081
摘要： A method and apparatus for hot-docking is disclosed. In one embodiment, a portable computer system includes a bus bridge and a bus coupled to the bus bridge. The bus may have one or more peripheral devices or peripheral interfaces coupled to it. The bus may also be coupled to a docking interface having a bus switch. The bus switch, when closed and the computer is coupled to a docking station, may couple the bus to a peripheral interface in a docking station. The bus switch may close responsive to docking, thereby completing the electrical coupling of the bus to the peripheral interface in the docking station. The closing of the bus switch may be controlled by the docking interface such that operations on the bus are not interrupted during the docking procedure.
摘要翻译： 公开了用于热对接的方法和装置。 在一个实施例中，便携式计算机系统包括总线桥和耦合到总线桥的总线。 总线可以具有耦合到其的一个或多个外围设备或外围接口。 总线也可以耦合到具有总线开关的对接接口。 总线开关在闭合并且计算机耦合到对接站时可将总线耦合到对接站中的外围接口。 总线开关可以响应于对接而关闭，从而完成总线到对接站中的外围接口的电耦合。 总线开关的关闭可以由对接接口控制，使得总线上的操作在对接过程期间不被中断。
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公开(公告)号：US20080042701A1
公开(公告)日：2008-02-21
申请号：US11459413
申请日：2006-07-24
申请人： Raphael Weiss , Richard E. Wahler , John D. Virzi
发明人： Raphael Weiss , Richard E. Wahler , John D. Virzi
IPC分类号： H03L7/00
CPC分类号： H05K1/0266 , H05K1/0268 , H05K1/18 , H05K2201/09927
摘要： A resistor/capacitor identification detection (RCID) circuit may provide system level identification of hardware (e.g. circuit board ID) through a single pin interface, by identifying up to a specified number of more than two quantized RC time constant states by measuring the discharge and charge times of an external RC circuit coupled to the single pin. The RCID circuit may initiate the discharge followed by a charging of the external RC circuit. The signal developed at the signal pin may be provided to the input of a threshold detector, with the threshold set at a specified percentage of a supply voltage used for operating the RCID circuit. The digitized output of the threshold detector may be used to gate a counter, after having been filtered through an input glitch rejection filter. A resolution of the counter may be determined by a high frequency clock used for clocking the counter. The numeric values of the charge and discharge times may be stored in data registers comprised in the RCID circuit.
摘要翻译： 电阻/电容器识别检测（RCID）电路可以通过单个引脚接口提供硬件（例如电路板ID）的系统级别识别，通过测量放电确定多达两个量化的RC时间常数状态， 连接到单个引脚的外部RC电路的充电时间。 RCID电路可以启动放电，然后对外部RC电路进行充电。 在信号引脚处产生的信号可以被提供给阈值检测器的输入端，阈值设定在用于操作RCID电路的电源电压的指定百分比。 阈值检测器的数字化输出可以在通过输入毛刺抑制滤波器滤波后用于对计数器进行选通。 计数器的分辨率可以由用于对计数器计时的高频时钟确定。 充电和放电时间的数值可以存储在RCID电路中包含的数据寄存器中。
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公开(公告)号：US06919703B2
公开(公告)日：2005-07-19
申请号：US10459169
申请日：2003-06-11
CPC分类号： G01P3/481
摘要： A system may include a tachometer reading unit and a PWM (Pulse Width Modulated) signal generator configured to generate a PWM signal. The tachometer reading unit may be configured to obtain a tachometer reading from a tachometer signal generated by a device powered by the PWM signal. The tachometer reading unit includes a register configured to store a value indicative of a maximum stretching duration. The tachometer reading unit is configured to update the register in response to receiving a new value of the maximum stretching duration. The tachometer reading unit may be configured to control the PWM signal generator to stretch a pulse in the PWM signal and to not stretch the pulse longer than the maximum stretching duration indicated by the register. The tachometer reading unit is configured to obtain the tachometer reading during the stretched pulse in the PWM signal.
摘要翻译： 系统可以包括转速计读取单元和被配置为产生PWM信号的PWM（脉宽调制）信号发生器。 转速计读取单元可以被配置为从由PWM信号供电的装置产生的转速计信号获得转速计读数。 转速计读取单元包括配置为存储指示最大拉伸持续时间的值的寄存器。 转速计读取单元被配置为响应于接收到最大拉伸持续时间的新值而更新寄存器。 转速计读取单元可以被配置为控制PWM信号发生器在PWM信号中拉伸脉冲，并且不延伸比由寄存器指示的最大拉伸持续时间更长的脉冲。 转速计读数单元配置为在PWM信号中拉伸脉冲期间获得转速计读数。
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公开(公告)号：US07631176B2
公开(公告)日：2009-12-08
申请号：US11459413
申请日：2006-07-24
CPC分类号： H05K1/0266 , H05K1/0268 , H05K1/18 , H05K2201/09927
摘要： A resistor/capacitor identification detection (RCID) circuit may provide system level identification of hardware (e.g. circuit board ID) through a single pin interface, by identifying up to a specified number of more than two quantized RC time constant states by measuring the discharge and charge times of an external RC circuit coupled to the single pin. The RCID circuit may initiate the discharge followed by a charging of the external RC circuit. The signal developed at the signal pin may be provided to the input of a threshold detector, with the threshold set at a specified percentage of a supply voltage used for operating the RCID circuit. The digitized output of the threshold detector may be used to gate a counter, after having been filtered through an input glitch rejection filter. A resolution of the counter may be determined by a high frequency clock used for clocking the counter. The numeric values of the charge and discharge times may be stored in data registers comprised in the RCID circuit.
摘要翻译： 电阻/电容器识别检测（RCID）电路可以通过单个引脚接口提供硬件（例如电路板ID）的系统级别识别，通过测量放电确定多达两个量化的RC时间常数状态， 连接到单个引脚的外部RC电路的充电时间。 RCID电路可以启动放电，然后对外部RC电路进行充电。 在信号引脚处产生的信号可以被提供给阈值检测器的输入端，阈值设定在用于操作RCID电路的电源电压的指定百分比。 阈值检测器的数字化输出可以在通过输入毛刺抑制滤波器滤波后用于对计数器进行选通。 计数器的分辨率可以由用于对计数器计时的高频时钟确定。 充电和放电时间的数值可以存储在RCID电路中包含的数据寄存器中。
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6.发明授权Enhancing security of a system via access by an embedded controller to a secure storage device 有权通过嵌入式控制器访问安全存储设备来提高系统的安全性公开(公告)号：US07917741B2
公开(公告)日：2011-03-29
申请号：US11733599
申请日：2007-04-10
CPC分类号： G06F21/575
摘要： System and method for performing pre-boot security verification in a system that includes a host processor and memory, an embedded microcontroller with an auxiliary memory, e.g., an on-chip ROM, or memory controlled to prohibit user-tampering with the contents of the memory, and one or more pre-boot security components coupled to the embedded microcontroller. Upon power-up, but before host processor boot-up, the embedded microcontroller accesses the auxiliary memory and executes the program instructions to verify system security using the one or more pre-boot security components. The one or more pre-boot security components includes at least one identity verification component, e.g., a smart card, or a biometric sensor, e.g., a fingerprint sensor, a retinal scanner, and/or a voiceprint sensor, etc., and/or at least one system verification component, e.g., TPM, to query the system for system state information, and verify that the system has not been compromised.
摘要翻译： 用于在包括主处理器和存储器的系统中执行预引导安全验证的系统和方法，具有辅助存储器的嵌入式微控制器，例如片上ROM或被控制以禁止用户篡改内容的内存的存储器 存储器以及耦合到嵌入式微控制器的一个或多个预引导安全组件。 上电后，但在主机处理器启动之前，嵌入式微控制器访问辅助存储器并执行程序指令，以使用一个或多个预引导安全组件来验证系统的安全性。 一个或多个预引导安全组件包括至少一个身份验证组件，例如智能卡或生物测定传感器，例如指纹传感器，视网膜扫描器和/或声纹印刷传感器等，和/ 或至少一个系统验证组件（例如TPM）来查询系统的系统状态信息，并验证系统是否未被泄露。
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7.发明申请Enhancing Security of a System Via Access by an Embedded Controller to A Secure Storage Device 有权通过嵌入式控制器访问安全存储设备来提高系统的安全性公开(公告)号：US20090327678A1
公开(公告)日：2009-12-31
申请号：US11733599
申请日：2007-04-10
IPC分类号： G06F15/177
CPC分类号： G06F21/575
摘要： System and method for performing pre-boot security verification in a system that includes a host processor and memory, an embedded microcontroller with an auxiliary memory, e.g., an on-chip ROM, or memory controlled to prohibit user-tampering with the contents of the memory, and one or more pre-boot security components coupled to the embedded microcontroller. Upon power-up, but before host processor boot-up, the embedded microcontroller accesses the auxiliary memory and executes the program instructions to verify system security using the one or more pre-boot security components. The one or more pre-boot security components includes at least one identity verification component, e.g., a smart card, or a biometric sensor, e.g., a fingerprint sensor, a retinal scanner, and/or a voiceprint sensor, etc., and/or at least one system verification component, e.g., TPM, to query the system for system state information, and verify that the system has not been compromised.
摘要翻译： 用于在包括主处理器和存储器的系统中执行预引导安全验证的系统和方法，具有辅助存储器的嵌入式微控制器，例如片上ROM或被控制以禁止用户篡改内容的内存的存储器 存储器以及耦合到嵌入式微控制器的一个或多个预引导安全组件。 上电后，但在主机处理器启动之前，嵌入式微控制器访问辅助存储器并执行程序指令，以使用一个或多个预引导安全组件来验证系统的安全性。 一个或多个预引导安全组件包括至少一个身份验证组件，例如智能卡或生物测定传感器，例如指纹传感器，视网膜扫描器和/或声纹印刷传感器等，和/ 或至少一个系统验证组件（例如TPM）来查询系统的系统状态信息，并验证系统是否未被泄露。
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8.发明申请Implementation of One Time Programmable Memory with Embedded Flash Memory in a System-on-Chip 有权在系统级芯片中实现具有嵌入式闪存的一次性可编程存储器公开(公告)号：US20090113114A1
公开(公告)日：2009-04-30
申请号：US11924826
申请日：2007-10-26
IPC分类号： G06F12/02
CPC分类号： G06F12/1433 , G06F2212/2022
摘要： System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller.
摘要翻译： 使用嵌入式闪存实现一次可编程（OTP）存储器的系统和方法。 片上系统（SoC）包括一个清除的闪存阵列，其中包括一个OTP块，包括一个最初被禁止的OTP写禁止字段，一个闪存控制器和一个控制器。 数据被写入OTP块，包括设置OTP写禁止字段以表示禁止对OTP块的后续写操作。 SoC是电源循环，并且作为响应，OTP块的至少一部分被锁存在易失性存储器中，包括基于OTP写禁止字段来断言OTP写禁止位，之后OTP块不可写。 响应于每次随后的电力循环，控制器保持复位，执行锁存，控制器从复位释放，并且现在写保护的闪存阵列被配置为由控制器控制。
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9.发明授权Implementation of one time programmable memory with embedded flash memory in a system-on-chip 有权在系统级芯片中实现具有嵌入式闪存的一次可编程存储器公开(公告)号：US07991943B2
公开(公告)日：2011-08-02
申请号：US11924826
申请日：2007-10-26
IPC分类号： G06F12/02
CPC分类号： G06F12/1433 , G06F2212/2022
摘要： System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller.
摘要翻译： 使用嵌入式闪存实现一次可编程（OTP）存储器的系统和方法。 片上系统（SoC）包括一个清除的闪存阵列，其中包括一个OTP块，包括一个最初被禁止的OTP写禁止字段，一个闪存控制器和一个控制器。 数据被写入OTP块，包括设置OTP写禁止字段以表示禁止对OTP块的后续写操作。 SoC是电源循环，并且作为响应，OTP块的至少一部分被锁存在易失性存储器中，包括基于OTP写禁止字段来断言OTP写禁止位，之后OTP块不可写。 响应于每次随后的电力循环，控制器保持复位，执行锁存，控制器从复位释放，并且现在写保护的闪存阵列被配置为由控制器控制。
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公开(公告)号：US4845575A
公开(公告)日：1989-07-04
申请号：US106552
申请日：1987-10-06
申请人： Richard E. Wahler
发明人： Richard E. Wahler
IPC分类号： G11B20/14
CPC分类号： G11B20/1403 , G11B20/1419
摘要： A floppy disk data separator includes a phase lock loop which locks onto a clock signal that is synchronized to the data stream being read from the disk. The clock signal is derived from a sync counter which is reset each time a data bit is received from the disk. The output of the sync counter is an edge delayed by 1/4 of a bit time. The next edge of the clock occurs each 1/2 bit time after that until the next data bit is received. These clock signals are phase compared with clock signals produced in the phase lock loop to synchronize the clock to the disk data. In another aspect of the invention, the phase lock loop is operated in either a low-gain or high-gain mode.
摘要翻译： 软盘数据分离器包括锁相环，其锁定到与从盘读取的数据流同步的时钟信号。 时钟信号是从同步计数器导出的，每当从磁盘接收到数据位时，该计数器被复位。 同步计数器的输出是延迟1/4位时间的边沿。 时钟的下一个边沿出现在每个1/2位时间之后，直到接收到下一个数据位。 这些时钟信号与在锁相环中产生的时钟信号进行相位比较，以将时钟同步到磁盘数据。 在本发明的另一方面，锁相环以低增益或高增益模式工作。
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