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公开(公告)号：US5359598A
公开(公告)日：1994-10-25
申请号：US77887
申请日：1993-06-15
摘要： An interface for coupling a standard telephone set to a distributed digital network for allowing digital voice communication over the distributed network such that the utilization of the distributed network is wholly transparent to the user. An interface is provided for each telephone set. Each interface includes a state machine, a coder/decoder and a digital tone generator. The state machine is responsive to analog control signals from the telephone set to generate digital control signals to be transmitted over the distributed network. The state machine is also responsive to digital control signals to control the digital waveform generator to generate supervisory tones which are relayed to the user by the telephone set. The state machine also monitors the operation of the corresponding state machine or machines in a normal or conference call and sends control signals to resolve inconsistent states of the respective state machines, resulting in a high degree of fault tolerance and independence from network protocols.
摘要翻译： 用于将标准电话机耦合到分布式数字网络以允许在分布式网络上进行数字语音通信的接口，使得分布式网络的利用对于用户是完全透明的。 为每个电话机提供一个接口。 每个接口包括状态机，编码器/解码器和数字乐音发生器。 状态机响应于来自电话机的模拟控制信号，以产生要在分布式网络上传输的数字控制信号。 状态机还响应于数字控制信号来控制数字波形发生器以产生由电话机中继给用户的监听音调。 状态机还监视正常或电话会议中对应的状态机或机器的操作，并发送控制信号以解决各状态机的不一致状态，导致高度的容错性和与网络协议的独立性。
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公开(公告)号：US5127001A
公开(公告)日：1992-06-30
申请号：US544114
申请日：1990-06-22
CPC分类号： H04L12/1813 , H04Q11/04
摘要： An arrangement for conducting a conference call over a distributed digital network in which, at each station connected to the conference call, only voice packets from the other stations connected to the conference call are received. To avoid the need for synchronization between stations connected to the conference call, a local time base is established to define a sequence of periodic intervals during which a single voice packet will be accepted from each station connected to the conference call. The interval is advantageously set to be approximately equal the sampling period for data in a received data packet which will be reasonably uniform for all stations on the network. This provides that, typically, a maximum of one data packet will be received from any selected station during a single time base interval. The time base interval can be adaptively adjusted by monitoring the transmission queues of the local or other stations connected to the conference call and the interval can be reduced if a transmission queue exceeds a predetermined length.
摘要翻译： 一种用于通过分布式数字网络进行电话会议的装置，其中在连接到电话会议的每个站点处仅接收来自连接到电话会议的其他站的语音分组。 为了避免对连接到会议呼叫的站之间的同步的需要，建立本地时基以定义周期性间隔的序列，在该周期间隔期间，将从连接到电话会议的每个站接收单个语音分组。 该间隔有利地被设置为近似等于接收的数据分组中的数据的采样周期，对于网络上的所有台站将是相当均匀的。 这规定，通常，在单个时基间隔期间，将从任何选择的站接收最多一个数据分组。 可以通过监视连接到电话会议的本地或其他站的传输队列来自适应地调整时基间隔，并且如果传输队列超过预定长度，则可以减小间隔。
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3.发明授权Electronic transmitter having a digital combiner circuit for transmitting multiple digital input signals simultaneously 失效电子发射机具有数字组合器电路，用于同时传输多个数字输入信号
公开(公告)号：US5631929A
公开(公告)日：1997-05-20
申请号：US437754
申请日：1995-05-09
CPC分类号： H04J13/0022 , H04B1/707 , H04J13/10
摘要： An electronic transmitter transmits multiple digital input signals simultaneously by including an encoding circuit, a digital combiner circuit, and a modulator circuit. The encoding circuit encodes each of the digital input signals as a sequence of "1" and "0" chips with all of the chip sequences being synchronized in parallel; the digital combiner circuit generates a signed multi-bit digital signal which indicates the number of "1" chips minus the number of "0" chips that concurrently occur in the synchronized chip sequences; and, the modulator circuit generates a sinusoidal analog signal with a phase and a peak amplitude that respectively indicate the sign and magnitude of the signed multi-bit digital signal.
摘要翻译： 电子发射器通过包括编码电路，数字组合器电路和调制器电路同时发送多个数字输入信号。 编码电路将每个数字输入信号编码为“1”和“0”码片的序列，其中所有码片序列并行同步; 数字组合器电路产生一个带符号的多位数字信号，该数字信号表示“1”码数减去同步码片序列中同时发生的“0”码片数; 并且调制器电路产生具有分别表示带符号的多位数字信号的符号和幅度的相位和峰值幅度的正弦模拟信号。
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公开(公告)号：US07539239B2
公开(公告)日：2009-05-26
申请号：US11533509
申请日：2006-09-20
CPC分类号： H04B1/70751 , H04B1/70735 , H04B1/7077
摘要： An apparatus and method of determining a signal code. The method comprising steps of acquiring and correlating a signal with a first code sequence. In response to the timing lock is achieved. Also in response to the signal correlation, an acknowledge from a receiver of the signal to a transmitter change to a second code sequence.
摘要翻译： 一种确定信号码的装置和方法。 该方法包括以下步骤：获取信号与第一代码序列相关联。 响应时序锁定实现。 同样响应于信号相关性，来自发射机的信号的接收机的确认变为第二码序列。
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公开(公告)号：US5084913A
公开(公告)日：1992-01-28
申请号：US559011
申请日：1990-07-26
IPC分类号： H04B1/707
CPC分类号： H04B1/707
摘要： A novel universal multi-mode programmable two-channel timing generator employs a plurality of counters and logic circuitry. An input chip counter is coupled for receiving system clock signals and producing chip strobe and other output timing signals which are programmably capable of generating different rates of operation and different data or PN rates on different channels as well as different I and O enable signals for dedicated tracking and timing signals. The signals produced are used for synchronous-sample or non-synchronous-sample operation in a simple fast acting circuit designed for VLSI implementation.
摘要翻译： 一种新型通用多模可编程双通道定时发生器采用多个计数器和逻辑电路。 输入芯片计数器被耦合用于接收系统时钟信号并产生芯片选通和其他输出定时信号，其可编程地能够产生不同的操作速率和不同信道上的不同数据或PN速率，以及用于专用的不同的I和O使能信号 跟踪和定时信号。 所产生的信号用于设计用于VLSI实现的简单快速电路中的同步采样或非同步采样操作。
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公开(公告)号：US5452327A
公开(公告)日：1995-09-19
申请号：US179600
申请日：1993-12-28
IPC分类号： H04B1/69
CPC分类号： H04B1/69
摘要： A programmable randomly tunable digital demodulator is provided with a carrier recovery loop and a PN code clock recovery loop each having a programmable digital loop filter coupled in series therein. Each digital loop filter is controlled by a timing control which is capable of controlling the carrier frequency tuning and the PN tuning frequency under the control of a microprocessor. A replica PN generator is programmed to produce an epoch signal when the transmitted carrier frequency and/or chipping rate is varied in a pseudorandom manner and is coupled to the timing controls so that the modulator replicates the received variable rate signals.
摘要翻译： 可编程随机可调谐数字解调器具有载波恢复环路和PN码时钟恢复环路，每个具有串行耦合的可编程数字环路滤波器。 每个数字环路滤波器由能够在微处理器控制下控制载波频率调谐和PN调谐频率的定时控制来控制。 当发送的载波频率和/或码片速率以伪随机方式变化并且耦合到定时控制时，复制PN发生器被编程为产生时标信号，使得调制器复制接收到的可变速率信号。
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7.发明授权Parallel processing based digital matched filter and error detector for a digital demodulator 失效用于数字解调器的基于并行处理的数字匹配滤波器和误差检测器
公开(公告)号：US5432813A
公开(公告)日：1995-07-11
申请号：US179637
申请日：1993-12-28
CPC分类号： H04B1/707
摘要： A high chipping rate digital demodulator circuit is coupled to the output of an analog front end communications receiver and comprises a low pass filter in each channel of the receiver. The filtered output is coupled to a plurality of parallel branches each having an analog to digital converter which converts a portion of an analog sample to digital format and effectively reduces the system clock rate by a ratio of the number of parallel branches. One set of parallel branches is coupled to an early-late clock error detector circuits and another set of parallel branches is coupled to data signal detector circuits and then combined before being applied to a clock error processing channel and a data signal phase error channel which maintains the lower clock rate of the parallel branches.
摘要翻译： 高切片率数字解调器电路耦合到模拟前端通信接收机的输出，并且包括接收机的每个通道中的低通滤波器。 经滤波的输出耦合到多个并行支路，每个并行支路具有模拟数字转换器，该模数转换器将模拟采样的一部分转换为数字格式，并通过并行分支数的比例有效地降低系统时钟速率。 一组并行分支耦合到早期时钟误差检测器电路，另一组并行分支耦合到数据信号检测器电路，然后在应用于时钟误差处理通道和数据信号相位误差信道之前组合 平行分支的较低时钟速率。
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公开(公告)号：US5062071A
公开(公告)日：1991-10-29
申请号：US559019
申请日：1990-07-26
IPC分类号： G06F7/62
CPC分类号： G06F7/62
摘要： A programmable digital gain accumulator is provided with a digital accumulator having approximately the same number of significant bits as the input data stream. The most significant bit of the input data stream is a sign bit coupled to a series cascade of flip-flops providing a selectable plurality of flip-flop delay times. The carry output of the accumulator is coupled to an input up/down counter having its output coupled to a multiplexor capable of selecting one of the carry outputs of the input up/down counter. The up or down count is controlled by the sign bit input from the sign bit delay circuit. The output of the multiplexor is inputted to an output up/down counter whose parallel output is the parallel synchronous digital gain command signal for direct use by a utilization device. The up or down count of the output up/down counter is controlled by a delayed sign input from the sign bit delay circuit.
摘要翻译： 可编程数字增益累加器具有与输入数据流大致相同数量的有效位的数字累加器。 输入数据流的最高有效位是耦合到提供可选择的多个触发器延迟时间的触发器的串联级联的符号位。 累加器的进位输出耦合到输入上/下计数器，其输出耦合到能够选择输入上/下计数器的进位输出中的一个的多路复用器。 向上或向下计数由符号位延迟电路输入的符号位控制。 多路复用器的输出被输入到并行输出是并行同步数字增益命令信号的输出上/下计数器，供直接由利用装置使用。 输出上/下计数器的向上或向下计数由来自符号位延迟电路的延迟符号输入控制。
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公开(公告)号：US5060180A
公开(公告)日：1991-10-22
申请号：US559014
申请日：1990-07-26
IPC分类号： H03H17/02 , H04B1/7085
CPC分类号： H04B1/7085 , H03H17/0294
摘要： A programmable second order loop filter is provided with first and second programmable scaling circuits arranged in parallel and having their outputs connected to first and second programmable one bit serial adders respectively. The output of the second programmable serial adder is coupled to the input of said first programmable serial adder and has its output coupled to the input of a programmable output stage so as to provide the ability to maintain the average quantization bit error to one-half of one bit of the least significant bit of the full loop filter width even though the output does not use or employ all of the significant bits.
摘要翻译： 可编程二阶环路滤波器被提供有并联布置的第一和第二可编程缩放电路，并且其输出分别连接到第一和第二可编程一位串行加法器。 第二可编程串行加法器的输出耦合到所述第一可编程串行加法器的输入，并且其输出耦合到可编程输出级的输入端，以便提供维持平均量化比特误差的一半的能力 即使输出不使用或使用所有有效位，全环路滤波器宽度的最低有效位的一位也是。
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公开(公告)号：US5134631A
公开(公告)日：1992-07-28
申请号：US559018
申请日：1990-07-26
CPC分类号： H03G3/3052 , H04K3/224
摘要： A novel programmable digital gain controller is provided for the automatic gain control loop of a communications receiver. The digital gain controller comprises a pair of digital detectors coupled to the real and imaginary components of a data stream for providing digital data magnitude output signals which are coupled to an adder whose output is coupled to a first input of a comparator having a second input coupled to a predetermined reference level command. The output of the comparator generates a digital error signal which is coupled to the input of a programmable gain accumulator having a second input proportional gain command so as to provide at the output of the programmable gain accumulator a digital gain command which may be coupled to a variable gain controlled amplifier which is connected in the input data stream of the channel of a communications receiver to provide a predetermine amplifier output level.
摘要翻译： 为通信接收机的自动增益控制环路提供了一种新颖的可编程数字增益控制器。 数字增益控制器包括耦合到数据流的实部和虚部的一对数字检测器，用于提供数字数据幅度输出信号，耦合到加法器，其输出耦合到具有第二输入耦合的比较器的第一输入 到预定的参考水平命令。 比较器的输出产生数字误差信号，该数字误差信号耦合到具有第二输入比例增益指令的可编程增益累加器的输入端，以便在可编程增益累加器的输出处提供数字增益命令，该数字增益命令可耦合到 可变增益控制放大器，其连接在通信接收机的信道的输入数据流中，以提供预定的放大器输出电平。
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