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公开(公告)号：US07725787B1
公开(公告)日：2010-05-25
申请号：US12235489
申请日：2008-09-22
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/31707
摘要： A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.
摘要翻译： 测试可编程设备的方法开始于根据应用的至少一部分编程可编程设备的至少一部分以产生编程电路，其中编程电路包括输入顺序元件和输出顺序元件。 该方法通过向编程的电路提供测试输入来继续。 该方法通过触发输入顺序元件来基于测试时钟的第一边临时存储测试输入来继续。 该方法继续通过触发输出顺序元件来临时存储基于测试时钟的第二边缘的编程电路的测试输出。 该方法通过根据测试时钟的第二个边沿捕获编程电路的测试输出来继续。
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公开(公告)号：US07454675B1
公开(公告)日：2008-11-18
申请号：US10970936
申请日：2004-10-22
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/31707
摘要： A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.
摘要翻译： 测试可编程设备的方法开始于根据应用的至少一部分编程可编程设备的至少一部分以产生编程电路，其中编程电路包括输入顺序元件和输出顺序元件。 该方法通过向编程的电路提供测试输入来继续。 该方法通过触发输入顺序元件来基于测试时钟的第一边临时存储测试输入来继续。 该方法继续通过触发输出顺序元件来临时存储基于测试时钟的第二边缘的编程电路的测试输出。 该方法通过根据测试时钟的第二个边沿捕获编程电路的测试输出来继续。
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3.发明授权Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration 有权内置自检（BIST）技术，用于使用部分重配置测试现场可编程门阵列（FPGA）公开(公告)号：US07302625B1
公开(公告)日：2007-11-27
申请号：US11284455
申请日：2005-11-21
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/3187 , G06F17/5054 , G06F2217/14
摘要： A Built-in Self Test (BIST) system is provided in a Field Programmable Gate Array (FPGA) that can adjust test signal patterns provided for testing after partial reconfiguration of the FPGA. The BIST system includes a decoder that monitors I/O signals and provides an output indicating when I/O signals change indicating partial reconfiguration has occurred. The decoder output is provided to a BIST test signal generator providing signals to an IP core of the FPGA as well as a BIST comparator for monitoring test results to change test signals depending on the partial configuration mode.
摘要翻译： 在现场可编程门阵列（FPGA）中提供了内置自测（BIST）系统，该阵列可以调整FPGA部分重新配置后提供的测试信号模式。 BIST系统包括一个监视I / O信号的解码器，并提供一个输出，指示何时I / O信号变化，表明发生了部分重新配置。 解码器输出提供给BIST测试信号发生器，向FPGA的IP内核提供信号，以及BIST比较器，用于监视测试结果，以根据部分配置模式更改测试信号。
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4.发明授权公开(公告)号：US07761755B1
公开(公告)日：2010-07-20
申请号：US11707360
申请日：2007-02-16
CPC分类号： G01R31/318516 , G01R31/31922
摘要： A circuit may be used for testing for faults in a programmable logic device. The circuit may include a clock generator coupled to receive a reference clock signal and generate a high speed clock signal; a circuit under test coupled to receive selected pulses of the high speed clock signal; and a programmable shift register coupled to receive a pulse width selection signal and generate an enable signal for selecting the pulses the high speed clock signal, wherein the pulse width of the enable signal is selected based upon the value of the pulse width selection signal. A method of testing for faults in a programmable logic device is also disclosed.
摘要翻译： 电路可用于测试可编程逻辑器件中的故障。 电路可以包括时钟发生器，其被耦合以接收参考时钟信号并产生高速时钟信号; 被测电路被耦合以接收高速时钟信号的选定脉冲; 以及可编程移位寄存器，其耦合以接收脉冲宽度选择信号并产生用于选择所述脉冲的使能信号，所述高速时钟信号基于所述脉冲宽度选择信号的值来选择所述使能信号的脉冲宽度。 还公开了可编程逻辑器件中的故障测试方法。
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