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公开(公告)号：US07725787B1
公开(公告)日：2010-05-25
申请号：US12235489
申请日：2008-09-22
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/31707
摘要： A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.
摘要翻译： 测试可编程设备的方法开始于根据应用的至少一部分编程可编程设备的至少一部分以产生编程电路，其中编程电路包括输入顺序元件和输出顺序元件。 该方法通过向编程的电路提供测试输入来继续。 该方法通过触发输入顺序元件来基于测试时钟的第一边临时存储测试输入来继续。 该方法继续通过触发输出顺序元件来临时存储基于测试时钟的第二边缘的编程电路的测试输出。 该方法通过根据测试时钟的第二个边沿捕获编程电路的测试输出来继续。
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公开(公告)号：US07454675B1
公开(公告)日：2008-11-18
申请号：US10970936
申请日：2004-10-22
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/31707
摘要： A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.
摘要翻译： 测试可编程设备的方法开始于根据应用的至少一部分编程可编程设备的至少一部分以产生编程电路，其中编程电路包括输入顺序元件和输出顺序元件。 该方法通过向编程的电路提供测试输入来继续。 该方法通过触发输入顺序元件来基于测试时钟的第一边临时存储测试输入来继续。 该方法继续通过触发输出顺序元件来临时存储基于测试时钟的第二边缘的编程电路的测试输出。 该方法通过根据测试时钟的第二个边沿捕获编程电路的测试输出来继续。
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公开(公告)号：US06891395B2
公开(公告)日：2005-05-10
申请号：US10853981
申请日：2004-05-25
申请人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
发明人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
IPC分类号： G01R31/28 , G01R31/3185 , G06F17/50 , H01L21/82 , H03K19/173
CPC分类号： G01R31/318519 , G06F17/5054
摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.
摘要翻译： 公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。 这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。
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公开(公告)号：US06817006B1
公开(公告)日：2004-11-09
申请号：US10104324
申请日：2002-03-22
申请人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
发明人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
IPC分类号： G06F1750
CPC分类号： G01R31/318519
摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.
摘要翻译： 公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。 这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。
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5.发明授权Methods of testing for shorts in programmable logic devices using relative quiescent current measurements 有权使用相对静态电流测量测试可编程逻辑器件中短路的方法公开(公告)号：US06920621B1
公开(公告)日：2005-07-19
申请号：US10644158
申请日：2003-08-20
CPC分类号： G06F11/24 , G01R31/3008 , G06F17/5027
摘要： Methods of testing for shorts (e.g., bridging defects) between interconnect lines in an integrated circuit. For example, in a design implemented in a programmable logic device (PLD), some interconnect lines are used and others are unused. To test for shorts between the used and unused interconnect lines, both used and unused interconnect lines are driven to a first logic level, and the leakage current is measured. The used interconnect lines are driven to a second logic level, while the unused lines remain at the first logic level. The current is again measured, and the difference between the two measurements is determined. If the difference exceeds a predetermined threshold, the device design combination is rejected. Some embodiments provide methods of testing for shorts between used and unused interconnect lines for a design targeted to a partially defective PLD.
摘要翻译： 测试集成电路中的互连线之间的短路（例如桥接缺陷）的方法。 例如，在可编程逻辑器件（PLD）中实现的设计中，使用一些互连线，而其他互连线未被使用。 为了测试使用和未使用的互连线之间的短路，使用的和未使用的互连线都被驱动到第一逻辑电平，并且测量泄漏电流。 所使用的互连线被驱动到第二逻辑电平，而未使用的线保持在第一逻辑电平。 再次测量电流，并确定两次测量之间的差异。 如果差异超过预定阈值，则设备组合被拒绝。 一些实施例提供了用于针对部分有缺陷的PLD的设计的在使用的和未使用的互连线之间的短路的测试方法。
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公开(公告)号：US06594610B1
公开(公告)日：2003-07-15
申请号：US09853351
申请日：2001-05-11
申请人： Shahin Toutounchi , Anthony P. Calderone , Zhi-Min Ling , Robert D. Patrie , Eric J. Thorne , Robert W. Wells
发明人： Shahin Toutounchi , Anthony P. Calderone , Zhi-Min Ling , Robert D. Patrie , Eric J. Thorne , Robert W. Wells
IPC分类号： G06F1900
CPC分类号： G01R31/318519 , G01R31/318342
摘要： A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.
摘要翻译： 新的测试方法使用现场可编程门阵列来模拟故障，而不是使用单独的计算机来模拟故障。 在一个实施例中，选择几个（例如，两个或三个）已知的良好FPGA。 在FPGA配置的设计中引入了一个故障。 将配置加载到FPGA中。 应用测试向量并评估结果。 如果结果与无故障配置的结果不同，则会发现故障。 这种方法的一个应用是评估故障覆盖。 公开了可用于本发明的故障模型。
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7.发明授权公开(公告)号：US07219314B1
公开(公告)日：2007-05-15
申请号：US10815483
申请日：2004-04-01
IPC分类号： G06F17/50 , G06F11/07 , G01R31/3181 , G01R31/02
CPC分类号： G01R31/318516
摘要： Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of “nanotechnology” and molecular-scale technology, or “molectronics.” Test methods identify alternative physical interconnect resources for each net required in the user design and, as need, reroute certain signal paths using the alternative resources. The test methods additionally limit testing to required resources so devices are not rejected as a result of testing performed on unused resources. The tests limit functional testing of used resources to those functions required in the user designs.
摘要翻译： 描述了在可编程逻辑器件（PLD）中实现客户设计的方法。 这些方法的缺陷容忍使得它们对采用“纳米技术”和分子规模技术或“molectronics”尤其有用。 测试方法识别用户设计中所需的每个网络的替代物理互连资源，并根据需要使用替代资源重新路由某些信号路径。 测试方法另外将测试限制为所需的资源，因为在未使用的资源上执行测试的结果，设备不会被拒绝。 测试将功能测试限制在用户设计中所需的功能。
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8.发明授权Application-specific methods useful for testing look up tables in programmable logic devices 有权应用程序特定的方法可用于测试可编程逻辑器件中的查找表公开(公告)号：US07007250B1
公开(公告)日：2006-02-28
申请号：US10388000
申请日：2003-03-12
IPC分类号： G06F17/50
CPC分类号： G01R31/318519 , G06F17/5054
摘要： Disclosed methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected customer designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given customer design without requiring the vendor to understand the design.
摘要翻译： 公开的利用包含至少一个局部缺陷的可编程逻辑器件的方法。 测试这些设备以确定其适用于实施可能不需要受缺陷影响的资源的所选客户设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对于给定客户设计的适用性，而不要求供应商了解设计。
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公开(公告)号：US6023565A
公开(公告)日：2000-02-08
申请号：US805378
申请日：1997-02-24
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for complicated application-specific circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. Next, the design database is transmitted over a data communications link such as the internet to a second computer, on which the compilation software resides. The design is then compiled and the resulting netlist is transmitted back to the originating computer. In one embodiment, a schematic symbol or HDL instantiation is also generated by the second computer, and transmitted back to the originating computer.
摘要翻译： 提供了一种指定设计参数的方法，用于配置可编程IC的电路。 描述电路的设计数据库在计算机屏幕显示器上以基于表格的格式显示。 设计数据库可以包括存储图，包括要放置在目标可编程IC中的位存储空间中的数据。 该设计数据库不需要电路的原理图或HDL描述，即使对于复杂的应用特定电路也是如此。 所需的参数由用户输入，通常使用切换按钮，下拉菜单或键盘输入。 然后将选定的参数输入设计数据库，从而根据所选参数配置设计数据库。 接下来，将设计数据库通过诸如因特网的数据通信链路传送到编译软件所在的第二计算机。 然后编译设计，并将所得到的网表传回原始计算机。 在一个实施例中，示意符号或HDL实例化也由第二计算机产生，并被发送回始发计算机。
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10.发明授权Methods of utilizing programmable logic devices having localized defects in application-specific products 有权在应用特定产品中利用具有局部缺陷的可编程逻辑器件的方法公开(公告)号：US07127697B1
公开(公告)日：2006-10-24
申请号：US10631461
申请日：2003-07-30
IPC分类号： G06F17/50
CPC分类号： G01R31/318516
摘要： Methods of utilizing partially defective PLDs, i.e., PLDs having localized defects. A partially defective PLD is tested for compatibility with a particular configuration bitstream. If the partially defective PLD is compatible with the bitstream (i.e., if the localized defect has no effect on the functionality of the design implemented by the bitstream), a product is made available that includes both the bitstream and the partially defective PLD. In some embodiments, the bitstream is stored in a memory device such as a programmable read-only memory (PROM). In some embodiments, the product is a chip set that includes the partially defective PLD and a separately-packaged PROM in which the bitstream has previously been stored. In some embodiments, the PROM is manufactured as part of the FPGA die.
摘要翻译： 利用部分有缺陷的PLD的方法，即具有局部缺陷的PLD。 测试部分有缺陷的PLD与特定配置比特流的兼容性。 如果部分有缺陷的PLD与比特流兼容（即，如果局部缺陷对由比特流实现的设计的功能没有影响），则产生包括比特流和部分缺陷的PLD的产品。 在一些实施例中，比特流存储在诸如可编程只读存储器（PROM）的存储器件中。 在一些实施例中，产品是包括部分有缺陷的PLD的芯片组和其中预先存储了比特流的单独封装的PROM。 在一些实施例中，PROM被制造为FPGA管芯的一部分。
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