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公开(公告)号：US07725787B1
公开(公告)日：2010-05-25
申请号：US12235489
申请日：2008-09-22
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/31707
摘要： A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.
摘要翻译： 测试可编程设备的方法开始于根据应用的至少一部分编程可编程设备的至少一部分以产生编程电路，其中编程电路包括输入顺序元件和输出顺序元件。 该方法通过向编程的电路提供测试输入来继续。 该方法通过触发输入顺序元件来基于测试时钟的第一边临时存储测试输入来继续。 该方法继续通过触发输出顺序元件来临时存储基于测试时钟的第二边缘的编程电路的测试输出。 该方法通过根据测试时钟的第二个边沿捕获编程电路的测试输出来继续。
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公开(公告)号：US07454675B1
公开(公告)日：2008-11-18
申请号：US10970936
申请日：2004-10-22
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/31707
摘要： A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.
摘要翻译： 测试可编程设备的方法开始于根据应用的至少一部分编程可编程设备的至少一部分以产生编程电路，其中编程电路包括输入顺序元件和输出顺序元件。 该方法通过向编程的电路提供测试输入来继续。 该方法通过触发输入顺序元件来基于测试时钟的第一边临时存储测试输入来继续。 该方法继续通过触发输出顺序元件来临时存储基于测试时钟的第二边缘的编程电路的测试输出。 该方法通过根据测试时钟的第二个边沿捕获编程电路的测试输出来继续。
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3.发明授权Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration 有权内置自检（BIST）技术，用于使用部分重配置测试现场可编程门阵列（FPGA）公开(公告)号：US07302625B1
公开(公告)日：2007-11-27
申请号：US11284455
申请日：2005-11-21
IPC分类号： G01R31/28
CPC分类号： G01R31/318519 , G01R31/3187 , G06F17/5054 , G06F2217/14
摘要： A Built-in Self Test (BIST) system is provided in a Field Programmable Gate Array (FPGA) that can adjust test signal patterns provided for testing after partial reconfiguration of the FPGA. The BIST system includes a decoder that monitors I/O signals and provides an output indicating when I/O signals change indicating partial reconfiguration has occurred. The decoder output is provided to a BIST test signal generator providing signals to an IP core of the FPGA as well as a BIST comparator for monitoring test results to change test signals depending on the partial configuration mode.
摘要翻译： 在现场可编程门阵列（FPGA）中提供了内置自测（BIST）系统，该阵列可以调整FPGA部分重新配置后提供的测试信号模式。 BIST系统包括一个监视I / O信号的解码器，并提供一个输出，指示何时I / O信号变化，表明发生了部分重新配置。 解码器输出提供给BIST测试信号发生器，向FPGA的IP内核提供信号，以及BIST比较器，用于监视测试结果，以根据部分配置模式更改测试信号。
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4.发明授权公开(公告)号：US07761755B1
公开(公告)日：2010-07-20
申请号：US11707360
申请日：2007-02-16
CPC分类号： G01R31/318516 , G01R31/31922
摘要： A circuit may be used for testing for faults in a programmable logic device. The circuit may include a clock generator coupled to receive a reference clock signal and generate a high speed clock signal; a circuit under test coupled to receive selected pulses of the high speed clock signal; and a programmable shift register coupled to receive a pulse width selection signal and generate an enable signal for selecting the pulses the high speed clock signal, wherein the pulse width of the enable signal is selected based upon the value of the pulse width selection signal. A method of testing for faults in a programmable logic device is also disclosed.
摘要翻译： 电路可用于测试可编程逻辑器件中的故障。 电路可以包括时钟发生器，其被耦合以接收参考时钟信号并产生高速时钟信号; 被测电路被耦合以接收高速时钟信号的选定脉冲; 以及可编程移位寄存器，其耦合以接收脉冲宽度选择信号并产生用于选择所述脉冲的使能信号，所述高速时钟信号基于所述脉冲宽度选择信号的值来选择所述使能信号的脉冲宽度。 还公开了可编程逻辑器件中的故障测试方法。
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公开(公告)号：US06891395B2
公开(公告)日：2005-05-10
申请号：US10853981
申请日：2004-05-25
申请人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
发明人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
IPC分类号： G01R31/28 , G01R31/3185 , G06F17/50 , H01L21/82 , H03K19/173
CPC分类号： G01R31/318519 , G06F17/5054
摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.
摘要翻译： 公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。 这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。
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6.发明授权Methods of testing for shorts in programmable logic devices using relative quiescent current measurements 有权使用相对静态电流测量测试可编程逻辑器件中短路的方法公开(公告)号：US06920621B1
公开(公告)日：2005-07-19
申请号：US10644158
申请日：2003-08-20
CPC分类号： G06F11/24 , G01R31/3008 , G06F17/5027
摘要： Methods of testing for shorts (e.g., bridging defects) between interconnect lines in an integrated circuit. For example, in a design implemented in a programmable logic device (PLD), some interconnect lines are used and others are unused. To test for shorts between the used and unused interconnect lines, both used and unused interconnect lines are driven to a first logic level, and the leakage current is measured. The used interconnect lines are driven to a second logic level, while the unused lines remain at the first logic level. The current is again measured, and the difference between the two measurements is determined. If the difference exceeds a predetermined threshold, the device design combination is rejected. Some embodiments provide methods of testing for shorts between used and unused interconnect lines for a design targeted to a partially defective PLD.
摘要翻译： 测试集成电路中的互连线之间的短路（例如桥接缺陷）的方法。 例如，在可编程逻辑器件（PLD）中实现的设计中，使用一些互连线，而其他互连线未被使用。 为了测试使用和未使用的互连线之间的短路，使用的和未使用的互连线都被驱动到第一逻辑电平，并且测量泄漏电流。 所使用的互连线被驱动到第二逻辑电平，而未使用的线保持在第一逻辑电平。 再次测量电流，并确定两次测量之间的差异。 如果差异超过预定阈值，则设备组合被拒绝。 一些实施例提供了用于针对部分有缺陷的PLD的设计的在使用的和未使用的互连线之间的短路的测试方法。
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公开(公告)号：US06594610B1
公开(公告)日：2003-07-15
申请号：US09853351
申请日：2001-05-11
申请人： Shahin Toutounchi , Anthony P. Calderone , Zhi-Min Ling , Robert D. Patrie , Eric J. Thorne , Robert W. Wells
发明人： Shahin Toutounchi , Anthony P. Calderone , Zhi-Min Ling , Robert D. Patrie , Eric J. Thorne , Robert W. Wells
IPC分类号： G06F1900
CPC分类号： G01R31/318519 , G01R31/318342
摘要： A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.
摘要翻译： 新的测试方法使用现场可编程门阵列来模拟故障，而不是使用单独的计算机来模拟故障。 在一个实施例中，选择几个（例如，两个或三个）已知的良好FPGA。 在FPGA配置的设计中引入了一个故障。 将配置加载到FPGA中。 应用测试向量并评估结果。 如果结果与无故障配置的结果不同，则会发现故障。 这种方法的一个应用是评估故障覆盖。 公开了可用于本发明的故障模型。
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公开(公告)号：US06817006B1
公开(公告)日：2004-11-09
申请号：US10104324
申请日：2002-03-22
申请人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
发明人： Robert W. Wells , Zhi-Min Ling , Robert D. Patrie , Vincent L. Tong , Jae Cho , Shahin Toutounchi
IPC分类号： G06F1750
CPC分类号： G01R31/318519
摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.
摘要翻译： 公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。 这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。
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公开(公告)号：US07917820B1
公开(公告)日：2011-03-29
申请号：US12123867
申请日：2008-05-20
申请人： Adarsh Pavle , Shahin Toutounchi
发明人： Adarsh Pavle , Shahin Toutounchi
IPC分类号： G01R31/28
CPC分类号： G01R31/318597 , G11C29/32 , G11C2029/0401 , G11C2029/3202
摘要： A method of testing of an embedded core of an integrated circuit (“IC”) is described. An IC has a hardwired embedded core and memory coupled to each other in the IC. The method includes writing a test vector to the memory while the embedded core is operative. The test vector is input from the memory to the embedded core to mimic scan chain input to the embedded core. A test result is obtained from the embedded core responsive in part to the test vector input.
摘要翻译： 描述了集成电路（“IC”）的嵌入式核心的测试方法。 IC具有在IC中彼此耦合的硬连线的嵌入式核心和存储器。 该方法包括在嵌入式核心工作时将测试向量写入存储器。 测试向量从存储器输入到嵌入式核心，以模拟到嵌入式核心的扫描链输入。 测试结果从嵌入式核心获得部分响应于测试矢量输入。
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公开(公告)号：US07219287B1
公开(公告)日：2007-05-15
申请号：US10955560
申请日：2004-09-29
CPC分类号： G01R31/31835 , G01R31/318516 , Y10S707/99953
摘要： A method and apparatus are disclosed that simplify and reduce the time required for detecting faults in a programmable device such as a programmable logic device (PLD) by utilizing fault coverage information corresponding to a plurality of test patterns for the PLD to reduce the set of potential faults. For one embodiment, each test pattern is designated as either passing or failing, the faults that are detectable by at least two failing test patterns and the faults that are not detectable by any passing test patterns are eliminated, and the remaining faults are diagnosed. For another embodiment, the faults detectable by each failing test pattern are diagnosed to generate corresponding fault sets, and the faults not common to the fault sets and not detectable by one or more of the failing test patterns are eliminated.
摘要翻译： 公开了一种方法和装置，其通过利用与PLD的多个测试模式对应的故障覆盖信息来简化和减少检测诸如可编程逻辑器件（PLD）的可编程设备中的故障所需的时间，以减少潜在的电位 故障 对于一个实施例，将每个测试模式指定为通过或失败，可以消除由至少两个故障测试模式可检测的故障，并且消除由任何通过的测试模式无法检测到的故障，并且诊断剩余的故障。 对于另一个实施例，可以诊断每个故障测试模式可检测到的故障以产生相应的故障集，并且消除由一个或多个故障测试模式不能检测到的故障集合不常见的故障。
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