Low power analog absolute differencing circuit and architecture
    1.
    发明授权
    Low power analog absolute differencing circuit and architecture 失效
    低功耗模拟绝对差分电路和架构

    公开(公告)号:US5530393A

    公开(公告)日:1996-06-25

    申请号:US442352

    申请日:1995-05-16

    CPC分类号: G06G7/22

    摘要: A low power analog absolute differencing circuit and architecture is disclosed. The circuit includes an integrating amplifier with an input node connected to a common integration line. The common integration line is connected to a set of analog comparison circuits to form an analog vector absolute differencing circuit row. Each of the analog comparison circuits compares a first analog signal to a second analog signal to produce an absolute difference signal. The absolute difference signal from each analog comparison circuit is transmitted in the form of charge drawn from the common integration line. The integrating amplifier provides an integration sum corresponding to the sum of the absolute difference signals. The analog absolute differencing architecture includes a set of analog vector absolute differencing circuit rows arranged to form an analog absolute difference computing array. The analog absolute difference computing array is loaded with a data block input array and a data frame input array. The data block input array inputs a first set of analog signals corresponding to a first set of data. The data frame input array inputs a second set of analog signals corresponding to a second set of data. The integrating amplifiers of the analog vector absolute differencing circuit rows of the analog absolute difference computing array constitute a distance integration array. A distance evaluation block takes as input the set of distances computed by the distance integration array and evaluates these distances to provide a single output, usually an address of a single row of the distance integration array.

    摘要翻译: 公开了一种低功耗模拟绝对差分电路和架构。 该电路包括具有连接到公共集成线的输入节点的积分放大器。 公共集成线连接到一组模拟比较电路,以形成模拟矢量绝对差分电路行。 每个模拟比较电路将第一模拟信号与第二模拟信号进行比较以产生绝对差信号。 来自每个模拟比较电路的绝对差信号以从公共集成线提取的电荷的形式传输。 积分放大器提供对应于绝对差信号之和的积分和。 模拟绝对差分架构包括一组模拟矢量绝对差分电路行,其布置成形成模拟绝对差分计算阵列。 模拟绝对差分计算阵列装载有数据块输入阵列和数据帧输入阵列。 数据块输入阵列输入对应于第一组数据的第一组模拟信号。 数据帧输入阵列输入对应于第二组数据的第二组模拟信号。 模拟绝对差分计算阵列的模拟矢量绝对差分电路行的积分放大器构成距离积分阵列。 距离评估块将由距离积分阵列计算的距离集合作为输入,并评估这些距离以提供单个输出,通常是距离积分阵列的单行的地址。

    Analog voltage-signal selector device
    2.
    发明授权
    Analog voltage-signal selector device 失效
    模拟电压信号选择器

    公开(公告)号:US5905387A

    公开(公告)日:1999-05-18

    申请号:US742978

    申请日:1996-11-01

    CPC分类号: G06N3/0635

    摘要: The present invention relates to an analog voltage-signal selector device of the type comprising at least one plurality of comparator circuits operating in parallel and each having at least a first and second input terminals and designed to receive respectively an analog voltage-comparison signal and analog voltage signals of predetermined value and at least one output terminal for digital voltage signals. This selector device also comprises at least one logic circuit having a plurality of input terminals each connected to a corresponding output terminal of the comparator circuits and at least one output terminal. Finally the selector incorporates at least one plurality of latches each having at least one input terminal connected to the output terminal of a corresponding comparator circuit and at least one drive terminal coupled to the output terminal of the logic circuit with each of the memory circuits having at least one output terminal corresponding to an output of the selector.

    摘要翻译: 本发明涉及一种模拟电压信号选择器装置,其类型包括至少一个并联工作的多个比较器电路,每个具有至少一个第一和第二输入端,并被设计成分别接收模拟电压比较信号和模拟 预定值的电压信号和用于数字电压信号的至少一个输出端子。 该选择器装置还包括具有多个输入端的至少一个逻辑电路,每个输入端连接到比较器电路的相应输出端和至少一个输出端。 最后,选择器包括至少一个多个锁存器,每个锁存器具有至少一个输入端子连接到对应的比较器电路的输出端子,以及耦合到逻辑电路的输出端子的至少一个驱动端子,每个存储器电路具有 对应于选择器的输出的至少一个输出端子。

    Low power analog absolute differencing circuit and architecture
    3.
    发明授权
    Low power analog absolute differencing circuit and architecture 失效
    低功耗模拟绝对差分电路和架构

    公开(公告)号:US5438293A

    公开(公告)日:1995-08-01

    申请号:US132447

    申请日:1993-10-04

    CPC分类号: G06G7/22

    摘要: A low power analog absolute differencing circuit includes an integrating amplifier with an input node connected to a common integration line. The common integration line is connected to a set of analog comparison circuits to form an analog vector absolute differencing circuit row. Each of the analog comparison circuits compares a first analog signal to a second analog signal to produce an absolute difference signal. The absolute difference signal from each analog comparison circuit is transmitted in the form of charge drawn from the common integration line. The integrating amplifier provides an integration sum corresponding to the sum of the absolute difference signals. The analog absolute differencing architecture includes a set of analog vector absolute differencing circuit rows arranged to form an analog absolute difference computing array. The analog absolute difference computing array is loaded with a data block input array and a data frame input array. The data block input array inputs a first set of analog signals corresponding to a first set of data. The data frame input array inputs a second set of analog signals corresponding to a second set of data. The integrating amplifiers of the analog vector absolute differencing circuit rows of the analog absolute difference computing array constitute a distance integration array. A distance evaluation block takes as input the set of distances computed by the distance integration array and evaluates these distances to provide a single output, usually an address of a single row of the distance integration array.

    摘要翻译: 低功率模拟绝对差分电路包括具有连接到公共集成线的输入节点的积分放大器。 公共集成线连接到一组模拟比较电路,以形成模拟矢量绝对差分电路行。 每个模拟比较电路将第一模拟信号与第二模拟信号进行比较以产生绝对差信号。 来自每个模拟比较电路的绝对差信号以从公共集成线提取的电荷的形式传输。 积分放大器提供对应于绝对差信号之和的积分和。 模拟绝对差分架构包括一组模拟矢量绝对差分电路行,其布置成形成模拟绝对差分计算阵列。 模拟绝对差分计算阵列装载有数据块输入阵列和数据帧输入阵列。 数据块输入阵列输入对应于第一组数据的第一组模拟信号。 数据帧输入阵列输入对应于第二组数据的第二组模拟信号。 模拟绝对差分计算阵列的模拟矢量绝对差分电路行的积分放大器构成距离积分阵列。 距离评估块将由距离积分阵列计算的距离集合作为输入,并评估这些距离以提供单个输出,通常是距离积分阵列的单行的地址。

    Method for identifying marking stripes of road lanes
    4.
    发明授权
    Method for identifying marking stripes of road lanes 失效
    识别道路标志条纹的方法

    公开(公告)号:US06212287B1

    公开(公告)日:2001-04-03

    申请号:US08951956

    申请日:1997-10-17

    IPC分类号: G06K900

    CPC分类号: G05D1/0246 G05D2201/0213

    摘要: A method, in a system for aiding the guidance of a vehicle, for identifying marking stripes of road lanes. A road image is subjected to a convolution operation with a mask matrix so as to identify discontinuities present in the image. The resulting convolved image is compared with a threshold value and a representation of the marking stripes is determined. The mask matrix is set in such a way as to eliminate at least partially the discontinuities which do not correspond to the marking stripes.

    摘要翻译: 一种用于辅助车辆引导的系统中用于识别道路标线的方法。 使用掩模矩阵对道路图像进行卷积运算,以识别图像中存在的不连续性。 将所得到的卷积图像与阈值进行比较,并确定标记条纹的表示。 掩模矩阵被设置为至少部分地消除不对应于标记条纹的不连续性。

    Hybrid multi-sensor biometric identification device
    5.
    发明授权
    Hybrid multi-sensor biometric identification device 有权
    混合多传感器生物识别装置

    公开(公告)号:US08073204B2

    公开(公告)日:2011-12-06

    申请号:US11967883

    申请日:2007-12-31

    IPC分类号: G06K9/00 G05B19/00

    CPC分类号: A61B5/1172 G06K9/00013

    摘要: An improved fingerprint sensing device is provided with multiple sensing apparatus, two or more of which operating on different sensing principles. For example, a capacitive sensor may be integrally formed with an optical sensor on a single substrate. Ideally, the multiple sensing apparatus are disposed such that they may sense nearly identical portions of a fingerprint simultaneously. A primary sensor may be employed to establish the identity of a user based on a fingerprint, while a secondary sensor may be employed to establish that the fingerprint is part of a live human (anti-spoofing). Integrated light sources may be provided to drive an optical sensor. The light sources may also provide visual cues for usage, and enhance the aesthetics of the device.

    摘要翻译: 改进的指纹感测装置设置有多个感测装置,其中两个或更多个操作在不同的感测原理上。 例如,电容传感器可以与单个基板上的光学传感器一体地形成。 理想地,多感测装置被布置成使得它们可以同时感测指纹的几乎相同的部分。 可以使用主传感器来基于指纹建立用户的身份,而可以采用辅助传感器来确定指纹是活人(反欺骗)的一部分。 可以提供集成的光源来驱动光学传感器。 光源还可以提供用于使用的视觉提示,并且增强设备的美观性。

    Integrated Leadframe And Bezel Structure And Device Formed From Same
    6.
    发明申请
    Integrated Leadframe And Bezel Structure And Device Formed From Same 有权
    集成的引线框和边框结构与设备相同

    公开(公告)号:US20100127366A1

    公开(公告)日:2010-05-27

    申请号:US12324869

    申请日:2008-11-27

    IPC分类号: H01L23/495 H01L21/71

    摘要: An integrated leadframe and bezel structure includes a planar carrier frame, a plurality of bonding leads, a die pad region, and a bezel structure. The bezel structure includes a bending portion shaped and disposed to facilitate a portion of said bezel structure being bent out of the plane of said carrier frame. A sensor IC may be secured to the die pad region, and wire bonds made to permit external connection to the sensor IC. The bezel structure includes portions which are bent such that their upper extent is in or above a sensing surface. The assembly is encapsulated, exposing on the top surface part of the bezel portions and the upper surface of the sensor IC, and on the bottom surface the contact pads. Two or more bezel portions may be provided, one or more on each side of the sensor IC.

    摘要翻译: 集成的引线框架和边框结构包括平面载体框架,多个键合引线,芯片焊盘区域和边框结构。 边框结构包括弯曲部分,该弯曲部分成形并设置成便于所述边框结构的一部分从所述载体框架的平面弯曲出来。 传感器IC可以固定到管芯焊盘区域,并且引线接合以允许外部连接到传感器IC。 边框结构包括弯曲的部分,使得它们的上部范围在感测表面中或上方。 组件被封装,暴露在边框部分的顶表面部分和传感器IC的上表面上,并且在底表面上暴露于接触垫。 可以提供两个或更多个边框部分,在传感器IC的每一侧上设置一个或多个边框部分。

    ELECTROSTATIC DISCHARGE PROTECTION OF A CAPACITIVE TYPE FINGERPRINT SENSING
    7.
    发明申请
    ELECTROSTATIC DISCHARGE PROTECTION OF A CAPACITIVE TYPE FINGERPRINT SENSING 失效
    静电放电保护电容式指纹感测

    公开(公告)号:US20060011997A1

    公开(公告)日:2006-01-19

    申请号:US11162861

    申请日:2005-09-27

    IPC分类号: H01L29/82

    摘要: A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input mode and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided for each amplifier by way of (1) a first capacitor plate that is placed vertically under the upper surface of a dielectric layer and is connected to the ungrounded amplifier input node, (2) a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and is connected to the ungrounded output node, and (3) an ungrounded fingertip whose fingerprint pattern is to be detected, which ungrounded fingertip is placed on the upper surface of the dielectric layer in close vertical spatial relation with the first and second capacitor plates. Electrostatic discharge protection relative to electrostatic potential that may be carried by the ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.

    摘要翻译: 平面指纹图案检测阵列包括以行/列配置布置的大量单独的皮肤距离感测单元。 每个感测单元包括具有不接地输入模式的放大器和未接地输出节点。 通过以下步骤为每个放大器提供对指纹图案敏感的输出到输入负反馈:(1)第一电容器板,其垂直放置在电介质层的上表面下方并连接到未接地的放大器输入节点 ,(2)第二电容器板,其垂直于电介质层的上表面放置在与第一电容器板紧密的水平空间关系上,并连接到未接地的输出节点,(3)指纹图案为未接地的指尖 要被检测到,哪个未接地的指尖被放置在与第一和第二电容器板紧密垂直空间关系的电介质层的上表面上。 通过在电介质层内放置多个接地的金属路径来空间地围绕第一和第二电容器板中的每一个来提供相对于静电电位的静电放电保护,这是通过不接地的指尖来承载的, 打扰指尖的未接地状态。

    Electrostatic discharge protection of a capacitive type fingerprint sensing array
    8.
    发明授权
    Electrostatic discharge protection of a capacitive type fingerprint sensing array 失效
    电容型指纹感测阵列的静电放电保护

    公开(公告)号:US06987871B2

    公开(公告)日:2006-01-17

    申请号:US10253841

    申请日:2002-09-23

    IPC分类号: G06K9/00

    摘要: A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input node and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided for each amplifier by way of (1) a first capacitor plate that is placed vertically under the upper surface of a dielectric layer and is connected to the ungrounded amplifier input node, (2) a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and is connected to the ungrounded output node, and (3) an ungrounded fingertip whose fingerprint pattern is to be detected, which ungrounded fingertip is placed on the upper surface of the dielectric layer in close vertical spatial relation with the first and second capacitor plates. Electrostatic discharge protection relative to electrostatic potential that may be carried by the ungrounded fingertip is provided by placing a number of grounded metal paths within the dielectric layer to spatially surround each of the first and second capacitor plates, this being done in a manner that does not disturb the ungrounded state of the fingertip.

    摘要翻译: 平面指纹图案检测阵列包括以行/列配置布置的大量单独的皮肤距离感测单元。 每个感测单元包括具有未接地输入节点和未接地输出节点的放大器。 通过以下步骤为每个放大器提供对指纹图案敏感的输出到输入负反馈:(1)第一电容器板,其垂直放置在电介质层的上表面下方并连接到未接地的放大器输入节点 ,(2)第二电容器板,其垂直于电介质层的上表面与第一电容器板呈水平空间关系地放置,并连接到未接地的输出节点,(3)指纹图案为未接地的指尖 要被检测到,哪个未接地的指尖被放置在与第一和第二电容器板紧密垂直空间关系的电介质层的上表面上。 通过在电介质层内放置多个接地的金属路径来空间地围绕第一和第二电容器板中的每一个来提供相对于静电电位的静电放电保护,这是通过不接地的指尖来承载的, 打扰指尖的未接地状态。

    Low-voltage, very-low-power conductance mode neuron
    9.
    发明授权
    Low-voltage, very-low-power conductance mode neuron 有权
    低电压,极低功率的电导模式神经元

    公开(公告)号:US06269352B1

    公开(公告)日:2001-07-31

    申请号:US09461674

    申请日:1999-12-14

    IPC分类号: G06F1518

    CPC分类号: G06N3/063 G06N3/0635

    摘要: A neural network including a number of synaptic weighting elements, and a neuron stage; each of the synaptic weighting elements having a respective synaptic input connection supplied with a respective input signal; and the neuron stage having inputs connected to the synaptic weighting elements, and being connected to an output of the neural network supplying a digital output signal. The accumulated weighted inputs are represented as conductances, and a conductance-mode neuron is used to apply nonlinearity and produce an output. The synaptic weighting elements are formed by memory cells programmable to different threshold voltage levels, so that each presents a respective programmable conductance; and the neuron stage provides for measuring conductance on the basis of the current through the memory cells, and for generating a binary output signal on the basis of the total conductance of the synaptic elements.

    摘要翻译: 包括许多突触加权元素和神经元阶段的神经网络; 每个突触加权元件具有被提供有相应输入信号的相应突触输入连接; 并且神经元级具有连接到突触加权元件的输入,并且连接到提供数字输出信号的神经网络的输出端。 累积的加权输入被表示为电导,并且使用电导模式神经元来应用非线性并产生输出。 突触加权元件由可编程为不同阈值电压电平的存储器单元形成,使得每个呈现相应的可编程电导; 并且神经元级基于通过存储器单元的电流提供测量电导,并且用于基于突触元件的总电导产生二进制输出信号。