公开(公告)号：US06233012B1

公开(公告)日：2001-05-15

申请号：US08964570

申请日：1997-11-05

申请人： Roberto Guerrieri ,  Marco Bisio ,  Marco Tartagni

发明人： Roberto Guerrieri ,  Marco Bisio ,  Marco Tartagni

IPC分类号： H04N314

CPC分类号： H04N5/378 ,  G11C5/063 ,  G11C7/06 ,  H04N5/357 ,  H04N5/3742

摘要： A circuit technique to reduce the input capacitance line of a charge integrator is described. This approach is particularly tailored for embedded read-out circuits in solid-state integrated sensors. An integrated charge amplifier described herein includes a generic amplifier element and a high speed buffer which drives a metal shield placed underneath the input line. The metal shield therefore follows the potential of the input line and thereby reduces the capacitance between the input line and ground.

摘要翻译： 描述了用于减小电荷积分器的输入电容线的电路技术。 这种方法特别针对固态集成传感器中的嵌入式读出电路。 本文所述的集成电荷放大器包括通用放大器元件和驱动设置在输入线下方的金属屏蔽的高速缓冲器。 因此，金属屏蔽件遵循输入线的电位，从而减小输入线和地之间的电容。

公开(公告)号：US06581134B2

公开(公告)日：2003-06-17

申请号：US09817804

申请日：2001-03-26

申请人： Alessandro Rocchi ,  Marco Bisio ,  Marco Pasotti ,  Pier Luigi Rolandi

发明人： Alessandro Rocchi ,  Marco Bisio ,  Marco Pasotti ,  Pier Luigi Rolandi

IPC分类号： G06F1200

CPC分类号： G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7211

摘要： A FLASH memory is organized in a plurality of physical sectors which may be split into a plurality of singularly addressable logic sectors. Each logic sector may include a memory space of a predetermined size and a chain pointer assuming a neutral value or a value pointing to a second logic sector associated with a respective chain pointer at the neutral value. Each logic sector may also include a status indicator assuming at least one of a first value if the logic sector is empty, a second value if the data therein belongs to the logic sector, a third value if the data does not belong to the logic sector, and a fourth value if the data has been erased. Further, each logic sector may include a remap pointer assuming the neutral value or a value pointing directly or indirectly to the chain pointer of a third logic sector.

摘要翻译： FLASH存储器被组织在多个物理扇区中，这些扇区可以被分成多个可单独寻址的逻辑扇区。 每个逻辑扇区可以包括预定大小的存储器空间和假定中性值的链指针或指向与中性值处的相应链指针相关联的第二逻辑扇区的值。 如果逻辑扇区为空，则每个逻辑扇区还可以包括状态指示符，如果其中的数据属于逻辑扇区，则假设第二值为第一值;如果数据不属于逻辑扇区，则第三值 ，如果数据已被擦除，则为第四个值。 此外，每个逻辑扇区可以包括假定中性值的重映射指针或直接或间接指向第三逻辑扇区的链指针的值。

公开(公告)号：US06622106B2

公开(公告)日：2003-09-16

申请号：US09833754

申请日：2001-04-11

申请人： Alessandro Rocchi ,  Marco Bisio ,  Guido De Sandre ,  Giovanni Guaitini ,  Marco Pasotti ,  Pier Luigi Rolandi

发明人： Alessandro Rocchi ,  Marco Bisio ,  Guido De Sandre ,  Giovanni Guaitini ,  Marco Pasotti ,  Pier Luigi Rolandi

IPC分类号： H03B500

CPC分类号： G01R31/2824

摘要： A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.

摘要翻译： 一种用于测试和校准集成振荡器电路的振荡频率的数字装置，所述测试和校准装置具有至少第一和第二控制参数，所述至少第一和第二控制参数对应于为集成振荡器寻找的振荡频率的预定值范围的极限值 并且其包括用于比较已知持续时间的信号和来自集成振荡器电路的信号的比较电路; 连接到比较电路的电路，用于产生来自集成振荡电路的信号的校准值; 以及用于强制将来自集成振荡器电路的信号的最终校准值存储到集成振荡器电路的存储和控制部分的电路。