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公开(公告)号：US06581134B2
公开(公告)日：2003-06-17
申请号：US09817804
申请日：2001-03-26
IPC分类号： G06F1200
CPC分类号： G06F12/0246 , G06F2212/7203 , G06F2212/7211
摘要： A FLASH memory is organized in a plurality of physical sectors which may be split into a plurality of singularly addressable logic sectors. Each logic sector may include a memory space of a predetermined size and a chain pointer assuming a neutral value or a value pointing to a second logic sector associated with a respective chain pointer at the neutral value. Each logic sector may also include a status indicator assuming at least one of a first value if the logic sector is empty, a second value if the data therein belongs to the logic sector, a third value if the data does not belong to the logic sector, and a fourth value if the data has been erased. Further, each logic sector may include a remap pointer assuming the neutral value or a value pointing directly or indirectly to the chain pointer of a third logic sector.
摘要翻译： FLASH存储器被组织在多个物理扇区中，这些扇区可以被分成多个可单独寻址的逻辑扇区。 每个逻辑扇区可以包括预定大小的存储器空间和假定中性值的链指针或指向与中性值处的相应链指针相关联的第二逻辑扇区的值。 如果逻辑扇区为空，则每个逻辑扇区还可以包括状态指示符，如果其中的数据属于逻辑扇区，则假设第二值为第一值;如果数据不属于逻辑扇区，则第三值 ，如果数据已被擦除，则为第四个值。 此外，每个逻辑扇区可以包括假定中性值的重映射指针或直接或间接指向第三逻辑扇区的链指针的值。
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2.发明授权Device for testing and calibrating the oscillation frequency of an integrated oscillator 有权用于测试和校准集成振荡器的振荡频率的装置公开(公告)号：US06622106B2
公开(公告)日：2003-09-16
申请号：US09833754
申请日：2001-04-11
申请人： Alessandro Rocchi , Marco Bisio , Guido De Sandre , Giovanni Guaitini , Marco Pasotti , Pier Luigi Rolandi
发明人： Alessandro Rocchi , Marco Bisio , Guido De Sandre , Giovanni Guaitini , Marco Pasotti , Pier Luigi Rolandi
IPC分类号： H03B500
CPC分类号： G01R31/2824
摘要： A digital device for testing and calibrating the oscillation frequency of an integrated oscillator circuit, the testing and calibrating device has as input at least first and second control parameters corresponding to limiting values of a predetermined range of values of the oscillation frequency sought for the integrated oscillator circuit, and it includes a comparison circuit for comparing a signal of known duration and a signal from the integrated oscillator circuit; a circuit connected to the comparison circuit, for generating calibration values for the signal from the integrated oscillator circuit; and a circuit for forcing storage of final calibration values of the signal from the integrated oscillator circuit into a storage and control section of the integrated oscillator circuit.
摘要翻译： 一种用于测试和校准集成振荡器电路的振荡频率的数字装置，所述测试和校准装置具有至少第一和第二控制参数，所述至少第一和第二控制参数对应于为集成振荡器寻找的振荡频率的预定值范围的极限值 并且其包括用于比较已知持续时间的信号和来自集成振荡器电路的信号的比较电路; 连接到比较电路的电路，用于产生来自集成振荡电路的信号的校准值; 以及用于强制将来自集成振荡器电路的信号的最终校准值存储到集成振荡器电路的存储和控制部分的电路。
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公开(公告)号：US06687167B2
公开(公告)日：2004-02-03
申请号：US10225513
申请日：2002-08-20
申请人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
发明人： Giovanni Guaitini , Marco Pasotti , Guido De Sandre , David Iezzi , Marco Poles , Pier Luigi Rolandi
IPC分类号： G11C1604
摘要： A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.
摘要翻译： 一种非易失性半导体存储器件，包括连接到行线和两个电源端子的输出。 每个基本级具有具有p沟道MOS晶体管的上部分支和具有n沟道MOS晶体管的下部分支。 为了允许逐行擦除存储器，而不必使用能够承受高电压的部件，每个基本级具有两个辅助MOS晶体管，即上部支路中的n沟道晶体管和 下分支。 以这种方式，可以以这种方式偏置基本级，在读取和编程阶段，上部分支将用作上拉和下部分支作为下拉，而在擦除阶段，上部分支作为 下拉和下部分支作为上拉。
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4.发明授权Embeddable flash memory system for non-volatile storage of code, data and bit-streams for embedded FPGA configurations 有权可嵌入式闪存系统，用于非易失性存储用于嵌入式FPGA配置的代码，数据和位流公开(公告)号：US07251705B2
公开(公告)日：2007-07-31
申请号：US10768743
申请日：2004-01-29
IPC分类号： G06F12/00
CPC分类号： G11C16/30
摘要： An application-specific embeddable flash memory having three content-specific I/O ports and delivering a peak read throughput of 1.2 GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit having a programming rate of 1 Mbyte/s for non-volatile storage of code, data, and embedded FPGA bit stream configurations. The test chip uses a NOR-type 0.18 μm flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 μm2.
摘要翻译： 具有三个特定于内容的I / O端口并具有1.2 GB / s的峰值读取吞吐量的特定于应用的嵌入式闪存。 该存储器与用于代码，数据和嵌入式FPGA位流配置的非易失性存储的具有1兆字节/秒的编程速率的专用自动编程门电压斜坡发生器电路组合。 测试芯片采用NOR型0.18 mum闪存嵌入式技术，具有1.8V电源，两个聚六金属和存储单元尺寸为0.35 mum 2。
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5.发明授权Circuit for parallel programming nonvolatile memory cells, with adjustable programming speed 有权并行编程电路非易失性存储单元，具有可编程速度
公开(公告)号：US6163483A
公开(公告)日：2000-12-19
申请号：US447531
申请日：1999-11-23
CPC分类号： G11C16/12
摘要： A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.
摘要翻译： 一种具有电流镜电路的电路，具有第一节点和第二节点，分别连接到可控电流源和连接到所选存储器单元的漏极端子的公共节点。 第一运算放大器具有连接到第一节点和第二节点的输入，以及连接到所选择的存储器单元的控制端子并形成电路输出的输出。 第二运算放大器具有连接到斜坡发生器的第一输入端，连接到电路输出端的第二输入端，以及连接到可控电流源的控制输入端的输出端。 因此，两个负反馈环路将所选择的存储单元的漏极端子保持在足以编程的电压值，并且以导致所选择的存储单元写入的斜坡电压馈送存储单元的控制端子。 在第二节点和公共节点之间存在偏置源，使得在读取期间也可以使用相同的电路。
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6.发明授权Method for multilevel programming of a nonvolatile memory, and a multilevel nonvolatile memory 有权用于非易失性存储器和多级非易失性存储器的多级编程的方法
公开(公告)号：US06011715A
公开(公告)日：2000-01-04
申请号：US185906
申请日：1998-11-03
CPC分类号： G11C11/5621 , G11C11/5628
摘要： A programming method for a nonvolatile memory includes the steps of: a) determining a current value of the threshold voltage; b) acquiring a target value of the threshold voltage; c) calculating a first number of gate voltage pulses necessary to take the threshold voltage from the current value to the target value; d) applying a second number of consecutive voltage pulses to the gate terminal of the cell, the second number being correlated to the first number and having a uniformly increasing amplitude; e) then measuring a current value of the threshold voltage; and repeating steps c) to e) until a final threshold value is obtained.
摘要翻译： 一种用于非易失性存储器的编程方法包括以下步骤：a）确定阈值电压的当前值; b）获取阈值电压的目标值; c）计算将阈值电压从当前值到目标值所需的第一数量的栅极电压脉冲; d）将第二数量的连续电压脉冲施加到所述单元的栅极端子，所述第二数量与所述第一数量相关并具有均匀增加的幅度; e）然后测量阈值电压的当前值; 并重复步骤c）至e），直到获得最终阈值。
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公开(公告)号：US06535428B2
公开(公告)日：2003-03-18
申请号：US09882535
申请日：2001-06-14
申请人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , Michele Quarantelli , Pier Luigi Rolandi
发明人： Marco Pasotti , Guido De Sandre , Giovanni Guaitini , David Iezzi , Marco Poles , Michele Quarantelli , Pier Luigi Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/28 , G11C7/062 , G11C7/14 , G11C11/5642
摘要： A sensing circuit for sensing a memory cell, the sensing circuit having a first circuit branch electrically connectable to the memory cell to receive a memory cell current, the first circuit branch having at least one first transistor that, when the first circuit branch is connected to the memory cell, is coupled thereto substantially in a cascode configuration. A bias current generator is operatively associated with the first transistor for forcing a bias current to flow therethrough.
摘要翻译： 一种用于感测存储单元的感测电路，所述感测电路具有可电连接到所述存储单元以接收存储单元电流的第一电路分支，所述第一电路支路具有至少一个第一晶体管，当所述第一电路支路连接到 存储器单元基本上以共源共栅配置耦合到存储器单元。 偏置电流发生器与第一晶体管可操作地相关联，以迫使偏置电流流过其中。
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公开(公告)号：US06473340B1
公开(公告)日：2002-10-29
申请号：US09699043
申请日：2000-10-27
IPC分类号： G11C1300
CPC分类号： G11C11/5642 , G11C16/28
摘要： A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.
摘要翻译： 一种读取电路，具有经由阵列位线连接到阵列存储单元的阵列分支，其内容将被读取; 通过参考位线连接到提供参考电流的电流发生器级的参考支路; 连接到阵列支路和参考支路的电流/电压转换器级，并且在阵列节点和参考节点处分别提供与分别在阵列支路中流动的电流相关联的阵列电位和参考电位， 在参考分支中; 连接到阵列节点的比较器级和用于比较阵列和参考电位的参考节点; 布置在所述阵列节点和所述比较器台之间并且可选择地可操作地采样和保持所述阵列电位的采样和保持级; 以及用于关闭阵列分支的关闭阶段。
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9.发明授权Device and method for programming nonvolatile memory cells with automatic generation of programming voltage 有权用于自动生成编程电压来编程非易失性存储单元的装置和方法公开(公告)号：US06466481B1
公开(公告)日：2002-10-15
申请号：US09438232
申请日：1999-11-12
IPC分类号： G11C1606
CPC分类号： G11C16/12
摘要： The device comprises a current mirror circuit having a first and a second node connected, respectively, to a constant current source and to a drain terminal of a memory cell to be programmed. A voltage generating circuit is connected to the first node to bias it at a constant reference voltage (VR); an operational amplifier has an inverting input connected to the first node, a non-inverting input connected to the second node, and an output connected to the control terminal of the memory cell. Thereby, the drain terminal of the memory cell is biased at the constant reference voltage, having a value sufficient for programming, and the operational amplifier and the memory cell form a negative feedback loop that supplies, on the control terminal of the memory cell, a ramp voltage (VPCX) that causes writing of the memory cell. The ramp voltage increases with the same speed as the threshold voltage and can thus be used to know when the desired threshold value is reached, and thus when programming must be stopped. The presence of a bias transistor between the second node and the memory cell enables use of the same circuit also during reading.
摘要翻译： 该器件包括电流镜电路，其具有分别连接到待编程的存储器单元的恒定电流源和漏极端子的第一和第二节点。 电压产生电路连接到第一节点以将其以恒定的参考电压（VR）偏置; 运算放大器具有连接到第一节点的反相输入端，连接到第二节点的非反相输入端，以及连接到存储器单元的控制端子的输出端。 因此，存储单元的漏极端子被偏置在具有足以编程的值的恒定参考电压，并且运算放大器和存储单元形成负反馈回路，其在存储单元的控制端上提供 导致存储单元写入的斜坡电压（VPCX）。 斜坡电压以与阈值电压相同的速度增加，因此可以用于知道什么时候达到期望的阈值，并且因此当必须停止编程时。 在第二节点和存储器单元之间存在偏置晶体管，在读取期间也可以使用相同的电路。
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10.发明授权公开(公告)号：US06195283B1
公开(公告)日：2001-02-27
申请号：US09076013
申请日：1998-05-11
IPC分类号： G11C700
CPC分类号： G11C27/005
摘要： For each memory cell to be programmed, the present threshold value of the cell is determined; the desired threshold value is acquired; the analog distance between the present threshold value and the desired threshold value is calculated; and a programming pulse is then generated, the duration of which is proportional to the analog distance calculated. The programming and reading cycle is repeated until the desired threshold is reached. By this means a time saving is obtained, owing to the reduction of the number of intermediate reading steps. The method permits programming in parallel and simultaneously of a plurality of cells of a memory array which is connected to a single word line and to different bit lines, each with a programming pulse the duration of which is proportional to the analog distance calculated for the same cell. The programming process is thus very fast, owing to parallel application of the programming and the saving in the intermediate reading cycles.
摘要翻译： 对于要编程的每个存储器单元，确定单元的当前阈值; 获取期望的阈值; 计算当前阈值与期望阈值之间的模拟距离; 然后产生编程脉冲，其持续时间与计算出的模拟距离成比例。 重复编程和读取周期，直到达到所需的阈值。 由于中间读取步骤数量的减少，可以节省时间。 该方法允许并行地编程存储器阵列的多个单元，其连接到单个字线和不同的位线，每个存储器阵列的编程脉冲的持续时间与为同一个字线计算的模拟距离成比例 细胞。 编程过程非常快，因为编程的并行应用和中间阅读周期的节省。
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