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    Method of timing verification and layout optimization
    7.
    发明申请
    Method of timing verification and layout optimization 审中-公开
    定时验证和布局优化方法

    公开(公告)号：US20070143723A1

    公开(公告)日：2007-06-21

    申请号：US11642725

    申请日：2006-12-21

    申请人： Yoshiyuki Kawakami

    发明人： Yoshiyuki Kawakami

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： In timing verification considering process variations in the fabrication of semiconductor integrated circuits, parasitic element extraction results are obtained with high accuracy by considering variations in interconnect configuration occurring randomly inside LSI to perform timing verification of worst-case or best-case simulation. For example, a plurality of capacitance libraries are prepared according to process variations in the fabrication of semiconductor integrated circuits, such as variations in interconnect width, interconnect film thickness and interlayer film thickness, and one is selected among these capacitance libraries properly according to the target layout. In this way, parasitic element extraction results for worst-case or best-case simulation can be obtained with high accuracy for the target layout.

    摘要翻译： 考虑到半导体集成电路制造中的工艺变化的定时验证，通过考虑在LSI内部随机发生的互连配置的变化来实现最坏情况或最佳情况模拟的定时验证，从而以高精度获得寄生元件提取结果。 例如，根据半导体集成电路的制造中的工艺变化制备多个电容库，例如互连宽度，互连膜厚度和层间膜厚度的变化，并且根据目标适当选择这些电容库 布局。 以这种方式，可以以目标布局的高精度获得最坏情况或最佳情况下的寄生元件提取结果。

    Semiconductor integrated circuit
    8.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US07541625B2

    公开(公告)日：2009-06-02

    申请号：US11883539

    申请日：2006-03-03

    申请人： Yoshiyuki Kawakami

    发明人： Yoshiyuki Kawakami

    IPC分类号： H01L21/768

    CPC分类号： H01L27/0203 ,  H01L21/31053 ,  H01L21/7684 ,  H01L23/5222 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： When dummy patterns are arranged to planarize LSI layout patterns, a plurality of dummy patterns 1 are arranged in a wiring layer in which signal wiring patterns 2 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 2. These dummy patterns 1 cross signal wiring patterns 3 formed in another vertically adjacent wiring layer to have an inclination angle of generally 45 degrees. A plurality of dummy patterns 13 are located in the wiring layer in which the signal wiring patterns 3 are formed, so as to be inclined at an angle of generally 45 degrees toward the associated signal wiring patterns 3. The dummy patterns 1 formed in one of the adjacent wiring layers cross the dummy patterns 13 formed in the other wiring layer at an angle of generally 90 degrees. This reduces fluctuations in wiring capacitance and equalizes fluctuations in the wiring capacitance to the maximum extent.

    摘要翻译： 当布置虚拟图形以平坦化LSI布局图案时，在其中形成信号布线图案2的布线层中布置多个虚设图案1，以便以相对于相关联的信号布线图案大致45度的角度倾斜 这些虚拟图形1在另一个垂直相邻布线层中形成的交叉信号布线图案3具有大致45度的倾斜角。 多个虚设图形13位于其中形成信号布线图案3的布线层中，以相对于相关联的信号布线图案3以大致45度的角度倾斜。虚设图案1形成为 相邻的布线层以一般为90度的角度与形成在另一布线层中的虚设图案13交叉。 这样可以减少布线电容的波动，并最大限度地均衡布线电容的波动。

    Semiconductor integrated circuit and method for designing the same
    9.
    发明授权
    Semiconductor integrated circuit and method for designing the same 失效
    半导体集成电路及其设计方法

    公开(公告)号：US06498515B2

    公开(公告)日：2002-12-24

    申请号：US10142969

    申请日：2002-05-13

    申请人： Yoshiyuki Kawakami ,  Nobufusa Iwanishi

    发明人： Yoshiyuki Kawakami ,  Nobufusa Iwanishi

    IPC分类号： H03K1920

    CPC分类号： H03K19/00323 ,  G06F17/505

    摘要： A logical design method for a semiconductor integrated circuit includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) counting how many times a path leading from each input terminal to an output terminal in every logic cell of the circuit has operated; d) calculating a degradation rate associated with the path leading from each said input terminal to the output terminal in each said logic cell on the critical path by reference to the number of times of operation obtained in the step c); and e) exchanging a connection to one of the input terminals of each said logic cell, which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path corresponding to a lower degradation rate than that of the critical path, by reference to the degradation rates obtained in the step d).

    摘要翻译： 一种用于半导体集成电路的逻辑设计方法包括以下步骤：a）产生逻辑电平的电路以满足给定的功能和规格; b）提取从步骤a）中产生的电路产生最长延迟的关键路径; c）计算从电路的每个逻辑单元中的每个输入端子到输出端子的路径的操作次数; d）通过参考步骤c）中获得的操作次数，计算在关键路径上的每个所述逻辑单元中从每个所述输入端子到输出端子的路径相关联的退化率; 以及e）通过与逻辑单元的另一个输入端子的连接来与每个所述逻辑单元的哪个终端与关键路径相关联的输入终端之一交换连接，该终端与另一路径相关联 通过参考在步骤d）中获得的降解速率降低到关键路径的降解速率。

    Semiconductor integrated circuit and method for designing the same
    10.
    发明授权
    Semiconductor integrated circuit and method for designing the same 有权

    公开(公告)号：US06396307B1

    公开(公告)日：2002-05-28

    申请号：US09573568

    申请日：2000-05-19

    申请人： Yoshiyuki Kawakami ,  Nobufusa Iwanishi

    发明人： Yoshiyuki Kawakami ,  Nobufusa Iwanishi

    IPC分类号： H03K1920

    CPC分类号： H03K19/00323 ,  G06F17/505

    摘要： A logical design method for a semiconductor integrated circuit includes the steps of: a) generating a circuit at a logical level so as to meet given functions and specifications; b) extracting a critical path, which will cause the longest delay, from the circuit generated in the step a); c) counting how many times a path leading from each input terminal to an output terminal in every logic cell of the circuit has operated; d) calculating a degradation rate associated with the path leading from each said input terminal to the output terminal in each said logic cell on the critical path by reference to the number of times of operation obtained in the step c); and e) exchanging a connection to one of the input terminals of each said logic cell, which terminal is associated with the critical path, with a connection to another one of the input terminals of the logic cell, which terminal is associated with another path corresponding to a lower degradation rate than that of the critical path, by reference to the degradation rates obtained in the step d).