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1.发明申请Power saving methods and apparatus to selectively enable cache bits based on known processor state 有权省电方法和装置，用于基于已知的处理器状态选择性地启用高速缓存位公开(公告)号：US20060200686A1
公开(公告)日：2006-09-07
申请号：US11073284
申请日：2005-03-04
IPC分类号： G06F1/26
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.
摘要翻译： 描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。 处理器以多种模式运行。 其中一种模式限制了可以获取并执行到较长长度指令的指令。 指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在获取标签行时存储指令地址和处理器操作模式状态信息。 处理器操作模式状态信息指示处理器的程序指定的操作模式。 处理器从指令缓存器中获取指令以执行。 作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取 取。
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公开(公告)号：US20060277397A1
公开(公告)日：2006-12-07
申请号：US11144206
申请日：2005-06-02
IPC分类号： G06F9/44
CPC分类号： G06F9/3844
摘要： A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.
摘要翻译： 微处理器包括两个分支历史表，并且被配置为使用第一个分支历史表来预测分支目标高速缓存中的命中的分支指令，并且使用第二个分支历史表来预测分支指令， 在分支目标缓存中丢失。 因此，第一分支历史表被配置为具有与分支目标高速缓存的访问速度匹配的访问速度，使得其预测信息相对于可能在微处理器的指令流水线的早期发生的分支目标高速缓存命中检测而及时可用。 因此，第二分支历史表仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。
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公开(公告)号：US20060236078A1
公开(公告)日：2006-10-19
申请号：US11106803
申请日：2005-04-14
申请人： Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges , Kenneth Dockser , Michael McIlvaine , Rodney Smith
发明人： Thomas Sartorius , James Dieffenderfer , Jeffrey Bridges , Kenneth Dockser , Michael McIlvaine , Rodney Smith
IPC分类号： G06F9/44
CPC分类号： G06F9/30072 , G06F9/3826 , G06F9/3838 , G06F9/384
摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.
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4.发明申请Branch target address cache storing two or more branch target addresses per index 审中-公开分支目标地址缓存，每个索引存储两个或更多个分支目标地址公开(公告)号：US20060218385A1
公开(公告)日：2006-09-28
申请号：US11089072
申请日：2005-03-23
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/3848
摘要： A Branch Target Address Cache (BTAC) stores at least two branch target addresses in each cache line. The BTAC is indexed by a truncated branch instruction address. An offset obtained from a branch prediction offset table determines which of the branch target addresses is taken as the predicted branch target address. The offset table may be indexed in several ways, including by a branch history, by a hash of a branch history and part of the branch instruction address, by a gshare value, randomly, in a round-robin order, or other methods.
摘要翻译： 分支目标地址缓存（BTAC）在每个高速缓存行中存储至少两个分支目标地址。 BTAC由截断的分支指令地址索引。 从分支预测偏移表获得的偏移确定哪个分支目标地址被采用为预测分支目标地址。 偏移表可以通过分支历史，分支历史和部分分支指令地址的散列，以循环次序或其他方法随机的gshare值被索引。
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公开(公告)号：US20070094475A1
公开(公告)日：2007-04-26
申请号：US11254873
申请日：2005-10-20
IPC分类号： G06F12/00
CPC分类号： G06F12/1063 , G06F12/1054 , G06F12/145 , Y02D10/13
摘要： A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.
摘要翻译： 处理系统可以包括被配置为在多个页面中存储数据的存储器，TLB和包括多个高速缓存行的存储器高速缓存。 存储器中的每个页面可以包括多行存储器。 当虚拟地址被呈现给高速缓存时，存储器高速缓存可以允许要从多条高速缓存行识别的匹配高速缓存行，匹配高速缓存行具有与虚拟地址匹配的匹配地址。 存储器高速缓存可以被配置为允许通过在高速缓存行的每一个中存储行的页面属性来允许位于匹配地址的页面的一个或多个页面属性从存储器高速缓存而不是从TLB检索， 的数据存储在缓存行中。
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公开(公告)号：US20060195830A1
公开(公告)日：2006-08-31
申请号：US11066957
申请日：2005-02-25
IPC分类号： G06F9/45
CPC分类号： G06F9/30149 , G06F8/447 , G06F9/382
摘要： Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One technique includes defining a granule to be equal to the smallest length instruction in the instruction set and defining the number of granules that compose the longest length instruction in the instruction set to be MAX. The technique further includes determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length, MAX−1, into the instruction string to the end of the embedded data. Upon predecoding of the padded instruction string, a predecoder maintains synchronization with the instructions in the padded instruction string even if embedded data is coincidentally encoded to resemble an existing instruction in the variable length instruction set.
摘要翻译： 公开了用于确保指令串的同步预解码的技术。 指令串包含来自可变长度指令集和嵌入数据的指令。 一种技术包括定义一个等于指令集中最小长度指令的粒子，并将构成指令集中最长指令的粒子数定义为MAX。 该技术还包括当程序被编译或组装成指令串并将长度为MAX-1的填充插入到嵌入数据的结尾的指令串中时，确定嵌入数据段的结束。 在预编译填充指令串时，即使嵌入数据被巧合地编码成类似于可变长度指令集中的现有指令，预解码器也保持与填充指令串中的指令的同步。
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7.发明申请Conditional instruction execution via emissary instruction for condition evaluation 有权有条件的指令通过使用指令执行条件评估公开(公告)号：US20060179288A1
公开(公告)日：2006-08-10
申请号：US11055919
申请日：2005-02-10
IPC分类号： G06F9/44
CPC分类号： G06F9/3867 , G06F9/30072 , G06F9/3017 , G06F9/30181 , G06F9/3824 , G06F9/3826
摘要： Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the operation. The emissary instruction is executed, while the base instruction is halted. The emissary instruction evaluates the condition and reports the condition evaluation back to the base instruction. Based on the condition evaluation, the base instruction is either launched into the pipeline for execution, or it is discarded (or a NOP, or null instruction, substituted for it). In either case, the dependencies of following instructions may be resolved.
摘要翻译： 通过转换条件指令来简化危险检测，条件指令可操作以在满足条件的情况下执行操作到可操作以评估条件的执行指令和用于执行操作的无条件基准指令。 在基本指令停止的情况下执行执行指令。 使者指令评估条件并将条件评估报告回基本指令。 基于条件评估，基本指令要么被启动到管道中才能执行，要么被丢弃（或者一个NOP或者空的指令代替它）。 在任一情况下，可以解决以下指令的依赖性。
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公开(公告)号：US20060123326A1
公开(公告)日：2006-06-08
申请号：US10995858
申请日：2004-11-22
IPC分类号： H03M13/03
CPC分类号： G06F9/3861 , G06F9/30152 , G06F9/3017 , G06F9/382
摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as “mispredicted not taken” with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.
摘要翻译： 在流水线处理器中，在将存储在高速缓存中的指令进行预解码之前，在流水线执行期间检测到未正确预解码的指令。 相应的指令在缓存中无效，并且强制将该指令作为分支指令进行求值。 特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被采用”。 这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。 然后重新获取的指令被正确预解码，写入高速缓存并执行。
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公开(公告)号：US20060190711A1
公开(公告)日：2006-08-24
申请号：US11061975
申请日：2005-02-18
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4486
摘要： A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of return addresses from the return stack. Popping multiple return addresses from the return stack permits the processor to pre-fetch the return address of the original calling procedure in a chain of successive procedure calls. In one embodiment, the return stack controller reads the number of return levels from a value embedded in the return instruction. A complementary compiler calculates the return level values for given return instructions and embeds those values in them at compile-time. In another embodiment, the return stack circuit dynamically tracks the number of return levels by counting the procedure calls (branches) in a chain of successive procedure calls.
摘要翻译： 处理器包括用于预测用于指令预取的过程返回地址的返回堆栈电路，其中返回堆栈控制器确定与给定返回指令相关联的返回电平的数量，并且从返回堆栈中弹出该返回地址的数量。 从返回堆栈弹出多个返回地址允许处理器在连续的过程调用链中预取原始调用过程的返回地址。 在一个实施例中，返回堆栈控制器从嵌入在返回指令中的值读取返回电平的数量。 补充编译器计算给定返回指令的返回值，并在编译时嵌入这些值。 在另一个实施例中，返回堆栈电路通过对连续过程调用链中的过程调用（分支）进行计数来动态地跟踪返回电平的数量。
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公开(公告)号：US20070067574A1
公开(公告)日：2007-03-22
申请号：US11233575
申请日：2005-09-21
申请人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith , Robert Clancy , Victor Augsburg
发明人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius , Rodney Smith , Robert Clancy , Victor Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
摘要翻译： 管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。 例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。 响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。 响应于解锁写入，第二个指针是高级的。 第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。 因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。
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