公开(公告)号：US09652237B2

公开(公告)日：2017-05-16

申请号：US14581081

申请日：2014-12-23

申请人： Roger Gramunt ,  Ramon Matas ,  Benjamin C. Chaffin ,  Neal S. Moyer ,  Rammohan Padmanabhan ,  Alexey P. Suprun ,  Matthew G. Smith

发明人： Roger Gramunt ,  Ramon Matas ,  Benjamin C. Chaffin ,  Neal S. Moyer ,  Rammohan Padmanabhan ,  Alexey P. Suprun ,  Matthew G. Smith

IPC分类号： G06F9/30 ,  G06F11/34

CPC分类号： G06F9/3016 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3855 ,  G06F9/3857 ,  G06F11/3024 ,  G06F11/34 ,  G06F11/3466 ,  G06F11/36 ,  G06F11/362 ,  G06F11/3636

摘要： A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution engine. The engine may include a PEBS unit with logic to increment a counter each time an instance of a designated micro-op is retired a reorder buffer, capture output DLA referenced by an instance of the micro-op that executes after the counter overflows, set a captured bit associated with a reorder buffer identifier for the instance of the micro-op, and store a PEBS record in a debug storage when the instance of the micro-op is retired from the reorder buffer. The designated micro-op references a DLA of a memory accessible to the processor.

公开(公告)号：US20160179541A1

公开(公告)日：2016-06-23

申请号：US14581081

申请日：2014-12-23

申请人： Roger Gramunt ,  Ramon Matas ,  Benjamin C. Chaffin ,  Neal S. Moyer ,  Rammohan Padmanabhan ,  Alexey P. Suprun ,  Matthew G. Smith

发明人： Roger Gramunt ,  Ramon Matas ,  Benjamin C. Chaffin ,  Neal S. Moyer ,  Rammohan Padmanabhan ,  Alexey P. Suprun ,  Matthew G. Smith

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3855 ,  G06F9/3857 ,  G06F11/3024 ,  G06F11/34 ,  G06F11/3466 ,  G06F11/36 ,  G06F11/362 ,  G06F11/3636

摘要： A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution engine. The engine may include a PEBS unit with logic to increment a counter each time an instance of a designated micro-op is retired a reorder buffer, capture output DLA referenced by an instance of the micro-op that executes after the counter overflows, set a captured bit associated with a reorder buffer identifier for the instance of the micro-op, and store a PEBS record in a debug storage when the instance of the micro-op is retired from the reorder buffer. The designated micro-op references a DLA of a memory accessible to the processor.

摘要翻译： 处理器包括用于无序执行引擎的精确事件采样（PEBS）期间无状态捕获数据线性地址（DLA）的逻辑。 引擎可以包括具有逻辑的PEBS单元，每次当指定的微操作的实例退休时，重新排序缓冲器，由在计数器溢出之后执行的微操作的实例引用的捕获输出DLA，递增计数器，设置 捕获的位与微操作的实例的重新排序缓冲器标识相关联，并且当微操作的实例从重排序缓冲器中退出时，将PEBS记录存储在调试存储器中。 指定的微操作参考处理器可访问的存储器的DLA。

公开(公告)号：US20160179533A1

公开(公告)日：2016-06-23

申请号：US14581285

申请日：2014-12-23

申请人： Roger Gramunt ,  Rammohan Padmanabhan ,  Ramon Matas ,  Neal S. Moyer ,  Benjamin C. Chaffin ,  Avinash Sodani ,  Alexey P. Suprun ,  Vikram S. Sundaram ,  Chung-Lun Chan ,  Gerardo A. Fernandez ,  Julio Gago ,  Michael S. Yang ,  Aditya Kesiraju

发明人： Roger Gramunt ,  Rammohan Padmanabhan ,  Ramon Matas ,  Neal S. Moyer ,  Benjamin C. Chaffin ,  Avinash Sodani ,  Alexey P. Suprun ,  Vikram S. Sundaram ,  Chung-Lun Chan ,  Gerardo A. Fernandez ,  Julio Gago ,  Michael S. Yang ,  Aditya Kesiraju

IPC分类号： G06F9/30 ,  G11C7/10 ,  G06F12/12 ,  G06F9/38 ,  G06F9/48

CPC分类号： G06F12/122 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/4806 ,  G06F2212/62

摘要： In one embodiment, a processor includes a frontend unit having an instruction decoder to receive and to decode instructions of a plurality of threads, an execution unit coupled to the instruction decoder to receive and execute the decoded instructions, and an instruction retirement unit having a retirement logic to receive the instructions from the execution unit and to retire the instructions associated with one or more of the threads that have an instruction or an event pending to be retired. The instruction retirement unit includes a thread arbitration logic to select one of the threads at a time and to dispatch the selected thread to the retirement logic for retirement processing.

摘要翻译： 在一个实施例中，处理器包括前端单元，前端单元具有用于接收和解码多个线程的指令的指令解码器，耦合到指令解码器以接收和执行解码指令的执行单元，以及退休指令 从执行单元接收指令并且退出与具有等待退休的指令或事件的一个或多个线程相关联的指令的逻辑。 指令退出单元包括线程仲裁逻辑，用于一次选择一个线程，并将所选线程发送到用于退出处理的退出逻辑。

公开(公告)号：US09891914B2

公开(公告)日：2018-02-13

申请号：US14684150

申请日：2015-04-10

申请人： Ramon Matas ,  Alexey P. Suprun ,  Roger Gramunt ,  Chung-Lun Chan ,  Rammohan Padmanabhan

发明人： Ramon Matas ,  Alexey P. Suprun ,  Roger Gramunt ,  Chung-Lun Chan ,  Rammohan Padmanabhan

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30036 ,  G06F9/30043 ,  G06F9/30192 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3842

摘要： An apparatus and method for performing an efficient scatter operation. For example, one embodiment of a processor comprises: an allocator unit to receive a scatter operation comprising a number of data elements and responsively allocate resources to execute the scatter operation; a memory execution cluster comprising at least a portion of the resources to execute the scatter operation, the resources including one or more store data buffers and one or more store address buffers; and a senior store pipeline to transfer store data elements from the store data buffers to system memory using addresses from the store address buffers prior to retirement of the scatter operation.