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公开(公告)号：US07663621B1
公开(公告)日：2010-02-16
申请号：US11556515
申请日：2006-11-03
CPC分类号： G06T15/04
摘要： Circuits, methods, and apparatus that perform cylindrical wrapping in software without the need for a dedicated hardware circuit. One example performs cylindrical wrapping in software running on shader hardware. In one specific example, the shader hardware is a unified shader that alternately processes geometry, vertex, and fragment information. This unified shader is formed using a number of single-instruction, multiple-data units. Another example provides a method of performing a cylindrical wrap that ensures that a correct texture portion is used for a triangle that is divided by a “seam” of the wrap. To achieve this, primitive vertices are sorted such that results are vertex order invariant. One vertex is selected as a reference. For the other vertices, a difference is found for each coordinate and a corresponding coordinate of the reference vertex. If the coordinates are near, no change is made. If the coordinates are distant, the coordinate is adjusted.
摘要翻译： 在软件中执行圆柱形包装而不需要专用硬件电路的电路，方法和装置。 一个例子是在着色器硬件上运行的软件中执行圆柱包装。 在一个具体的例子中，着色器硬件是一个统一的着色器，交替地处理几何，顶点和片段信息。 这个统一着色器是使用多个单指令多数据单元形成的。 另一个例子提供了一种执行圆柱形包装的方法，该方法确保将正确的纹理部分用于由包裹的“接缝”划分的三角形。 为了实现这一点，原始顶点被排序，使得结果是顶点顺序不变的。 选择一个顶点作为参考。 对于其他顶点，对于每个坐标和参考顶点的相应坐标找到一个差异。 如果坐标靠近，则不进行任何更改。 如果坐标较远，则调整坐标。
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2.发明授权Apparatus and method for debugging a graphics processing unit in response to a debug instruction 有权响应于调试指令调试图形处理单元的装置和方法公开(公告)号：US07711990B1
公开(公告)日：2010-05-04
申请号：US11302952
申请日：2005-12-13
IPC分类号： G06F11/00
CPC分类号： G06F11/3648
摘要： A system includes a graphics processing unit with a processor responsive to a debug instruction that initiates the storage of execution state information. A memory stores the execution state information. A central processing unit executes a debugging program to analyze the execution state information.
摘要翻译： 系统包括具有处理器的图形处理单元，该处理器响应于启动执行状态信息的存储的调试指令。 存储器存储执行状态信息。 中央处理单元执行调试程序以分析执行状态信息。
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3.发明授权Method and apparatus for loop and branch instructions in a programmable graphics pipeline 有权可编程图形管道中循环和分支指令的方法和装置公开(公告)号：US06825843B2
公开(公告)日：2004-11-30
申请号：US10302411
申请日：2002-11-22
IPC分类号： G06T1500
CPC分类号： G06T15/005 , G06F9/3017 , G06F9/325 , G06F9/3853
摘要： A method and apparatus for executing loop and branch program instructions in a programmable graphics shader. The programmable graphics shader converts a sequence of instructions comprising a portion of a shader program and selects a first set of fragments to be processed. Subsequent sequences of instructions are converted until all of the instructions comprising the shader program have been executed on the first set of fragments. Each remaining set of fragments is processed by the shader program until all of the fragments are processed in the same manner. Furthermore, the instructions can contain one or more loop or branch program instructions that are conditionally executed. Additionally, when instructions within a loop as defined by a loop instruction are being executed a current loop count is pipelined through the programmable graphics shader and used as an index to access graphics memory.
摘要翻译： 一种用于在可编程图形着色器中执行循环和分支程序指令的方法和装置。 可编程图形着色器转换包括着色器程序的一部分的指令序列，并选择要处理的第一组片段。 随后的指令序列被转换，直到包括着色器程序的所有指令已经在第一组碎片上被执行。 每个剩余的片段由着色器程序处理，直到所有片段以相同的方式处理。 此外，指令可以包含有条件地执行的一个或多个循环或分支程序指令。 另外，当正在执行由循环指令定义的循环内的指令时，当前循环计数通过可编程图形着色器流水线并用作访问图形存储器的索引。
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4.发明授权Method and system for improving data coherency in a parallel rendering system 有权用于提高并行渲染系统中数据一致性的方法和系统公开(公告)号：US08379033B2
公开(公告)日：2013-02-19
申请号：US13399458
申请日：2012-02-17
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译： 公开了一种用于提高并行渲染系统中数据一致性的方法和系统。 具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳 的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。
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5.发明授权Generating event signals for performance register control using non-operative instructions 有权使用非操作指令生成用于性能寄存器控制的事件信号公开(公告)号：US07809928B1
公开(公告)日：2010-10-05
申请号：US11313872
申请日：2005-12-20
申请人： Roger L. Allen , Brett W. Coon , Ian A. Buck , John R. Nickolls
发明人： Roger L. Allen , Brett W. Coon , Ian A. Buck , John R. Nickolls
CPC分类号： G06T1/20 , G06F9/30072 , G06F9/30076 , G06F11/3466 , G06F2201/86 , G06F2201/865 , G06F2201/88
摘要： One embodiment of an instruction decoder includes an instruction parser configured to process a first non-operative instruction and to generate a first event signal corresponding to the first non-operative instruction, and a first event multiplexer configured to receive the first event signal from the instruction parser, to select the first event signal from one or more event signals and to transmit the first event signal to an event logic block. The instruction decoder may be implemented in a multithreaded processing unit, such as a shader unit, and the occurrences of the first event signal may be tracked when one or more threads are executed within the processing unit. The resulting event signal count may provide a designer with a better understanding of the behavior of a program, such as a shader program, executed within the processing unit, thereby facilitating overall processing unit and program design.
摘要翻译： 指令解码器的一个实施例包括：指令解析器，被配置为处理第一非操作指令并产生对应于第一非操作指令的第一事件信号;以及第一事件多路复用器，被配置为从指令接收第一事件信号 解析器，以从一个或多个事件信号中选择第一事件信号，并将第一事件信号发送到事件逻辑块。 指令解码器可以在诸如着色器单元的多线程处理单元中实现，并且当在处理单元内执行一个或多个线程时，可以跟踪第一事件信号的出现。 所得到的事件信号计数可以使设计者更好地理解在处理单元内执行的诸如着色器程序之类的程序的行为，从而有助于整体处理单元和程序设计。
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公开(公告)号：US07439979B1
公开(公告)日：2008-10-21
申请号：US10985285
申请日：2004-11-10
申请人： Roger L. Allen , Chad D. Walker , Rui M. Bestos
发明人： Roger L. Allen , Chad D. Walker , Rui M. Bestos
CPC分类号： G06T1/20
摘要： A shader having a cache memory for storing program instructions is described. The cache memory beneficially stores both current programming instructions for a fragment program being run and “look-ahead” programming instructions. The cache memory supports a scheduler that forms program commands that control programmable processing stations. The cache memory can store multiple programming instructions for a plurality of shaders. If the cache memory does not include the desired programming instructions, a miss is asserted and a scheduler (instruction processor) recovers the programming instructions to be run. Beneficially, the scheduler recovers additional programming instructions to support the look-ahead programming. The cache memory stores program instructions by cachelines, where each cacheline comprises a plurality of programming instructions. The cache memory can also store program identifiers.
摘要翻译： 描述了具有用于存储程序指令的高速缓冲存储器的着色器。 高速缓冲存储器有利地存储当前正在运行的片段程序和“先行”编程指令的当前编程指令。 高速缓冲存储器支持一个调度器，其形成控制可编程处理站的程序命令。 高速缓冲存储器可以存储多个着色器的多个编程指令。 如果高速缓冲存储器不包含所需的编程指令，则认定未命中，并且调度器（指令处理器）恢复要运行的编程指令。 有利地，调度器恢复附加的编程指令以支持预先编程。 缓存存储器通过高速缓存存储器存储程序指令，其中每个高速缓存行包括多个编程指令。 缓存存储器还可以存储程序标识符。
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7.发明申请Method for parallel fine rasterization in a raster stage of a graphics pipeline 有权在图形管道的光栅阶段中并行精细光栅化的方法公开(公告)号：US20070296725A1
公开(公告)日：2007-12-27
申请号：US11474027
申请日：2006-06-23
申请人： Walter R. Steiner , Franklin C. Crow , Craig M. Wittenbrink , Roger L. Allen , Douglas A. Voorhies
发明人： Walter R. Steiner , Franklin C. Crow , Craig M. Wittenbrink , Roger L. Allen , Douglas A. Voorhies
IPC分类号： G06F15/80
CPC分类号： G06T11/40 , G06T15/005
摘要： In a raster stage of a graphics processor, a method for parallel fine rasterization. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level to generate a plurality of tiles of pixels. The titles are subsequently rasterized at a second level by allocating the tiles to an array of parallel second-level rasterization units to generate covered pixels. The covered pixels are then output for rendering operations in a subsequent stage of the graphics processor.
摘要翻译： 在图形处理器的光栅阶段，一种并行精细光栅化的方法。 该方法包括在图形处理器的光栅级中接收用于光栅化的图形基元。 图形原语在第一级被光栅化以生成多个像素块。 随后通过将瓦片分配到并行的第二级光栅化单元的阵列来生成被覆盖的像素，随后将标题在第二级光栅化。 然后，在图形处理器的后续阶段输出被覆盖像素进行渲染操作。
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8.发明授权Method for parallel fine rasterization in a raster stage of a graphics pipeline 有权在图形管道的光栅阶段中并行精细光栅化的方法公开(公告)号：US08928676B2
公开(公告)日：2015-01-06
申请号：US11474027
申请日：2006-06-23
申请人： Walter R. Steiner , Franklin C. Crow , Craig M. Wittenbrink , Roger L. Allen , Douglas A. Voorhies
发明人： Walter R. Steiner , Franklin C. Crow , Craig M. Wittenbrink , Roger L. Allen , Douglas A. Voorhies
CPC分类号： G06T11/40 , G06T15/005
摘要： In a raster stage of a graphics processor, a method for parallel fine rasterization. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level to generate a plurality of tiles of pixels. The titles are subsequently rasterized at a second level by allocating the tiles to an array of parallel second-level rasterization units to generate covered pixels. The covered pixels are then output for rendering operations in a subsequent stage of the graphics processor.
摘要翻译： 在图形处理器的光栅阶段，一种并行精细光栅化的方法。 该方法包括在图形处理器的光栅级中接收用于光栅化的图形基元。 图形原语在第一级被光栅化以生成多个像素块。 随后通过将瓦片分配到并行的第二级光栅化单元的阵列来生成被覆盖的像素，随后将标题在第二级光栅化。 然后，在图形处理器的后续阶段输出被覆盖像素进行渲染操作。
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公开(公告)号：US08253748B1
公开(公告)日：2012-08-28
申请号：US11290764
申请日：2005-11-29
申请人： Roger L. Allen , Brett W. Coon
发明人： Roger L. Allen , Brett W. Coon
IPC分类号： G06F15/00
CPC分类号： G06F11/3466 , G06F2201/86 , G06F2201/88
摘要： One embodiment of a system for collecting performance data for a multithreaded processing unit includes a plurality of independent performance registers, each configured to count hardware-based and/or software-based events. Functional blocks within the multithreaded processing unit are configured to generate various event signals, and subsets of the events are selected and used to generate one or more functions, each of which increments one of the performance registers. By accessing the contents of the performance registers, a user may observe and characterize the behavior of the different functional blocks within the multithreaded processing unit when one or more threads are executed within the processing unit. The contents of the performance registers may also be used to modify the behavior of the program running on the multithreaded processing unit, to modify a global performance register or to trigger an interrupt.
摘要翻译： 用于收集多线程处理单元的性能数据的系统的一个实施例包括多个独立性能寄存器，每个独立性能寄存器被配置为对基于硬件和/或基于软件的事件进行计数。 多线程处理单元中的功能块被配置为生成各种事件信号，并且事件的子集被选择并用于生成一个或多个功能，每个功能增加一个性能寄存器。 通过访问性能寄存器的内容，当在处理单元内执行一个或多个线程时，用户可以观察和表征多线程处理单元内的不同功能块的行为。 性能寄存器的内容也可用于修改在多线程处理单元上运行的程序的行为，修改全局性能寄存器或触发中断。
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10.发明授权Apparatus and method for serial save and restore of graphics processing unit state information 有权用于串行保存和恢复图形处理单元状态信息的装置和方法公开(公告)号：US08212824B1
公开(公告)日：2012-07-03
申请号：US11313086
申请日：2005-12-19
申请人： Roger L. Allen , Nitij Mangal
发明人： Roger L. Allen , Nitij Mangal
IPC分类号： G06F15/16
CPC分类号： G06F9/461
摘要： A graphics processing unit includes a first processing controller controlling a first set of multi-threaded processors. A second processing controller controls a second set of multi-threaded processors. A serial bus connects the first processing controller to the second processing controller. The first processing controller gathers first state information from the first set of multi-threaded processors in response to a context switch token and then passes the context switch token over the serial bus to the second processing controller. The second processing controller gathers second state information from the second set of multi-threaded processors in response to the context switch token.
摘要翻译： 图形处理单元包括控制第一组多线程处理器的第一处理控制器。 第二处理控制器控制第二组多线程处理器。 串行总线将第一处理控制器连接到第二处理控制器。 第一处理控制器响应于上下文切换令牌从第一组多线程处理器收集第一状态信息，然后将串行总线上的上下文切换令牌传递给第二处理控制器。 响应于上下文切换令牌，第二处理控制器从第二组多线程处理器收集第二状态信息。
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