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    Systems for integrating peripheral devices with hand-held computing devices
    1.
    发明申请
    Systems for integrating peripheral devices with hand-held computing devices 审中-公开
    将外围设备与手持计算设备集成的系统

    公开(公告)号：US20070146985A1

    公开(公告)日：2007-06-28

    申请号：US11515434

    申请日：2006-08-31

    申请人： Roger Mick ,  Vincent Turco ,  Michael Walsh ,  Daniel Dolan ,  Eric Eckstein

    发明人： Roger Mick ,  Vincent Turco ,  Michael Walsh ,  Daniel Dolan ,  Eric Eckstein

    IPC分类号： G06F1/16

    CPC分类号： G06F1/1632

    摘要： Embodiments of systems include a capsule that houses one or more peripheral devices, such as radios, capable of being used with hand-held computing devices such as RFID tag readers. A receptacle can be mounted on the hand-held computing device. The receptacle receives the capsule. Electrical connectors on the capsule and the receptacle mate when the receptacle is received by the receptacle, to electrically connect the peripheral device and the hand-held computing device. A seal is provided to prevent infiltration of water, dust, and other contaminates into the electrical connectors. A portion of the capsule is exposed when the capsule is located in the receptacle, to accommodate external antennas, connectors, optical ports, etc. that may be required by the peripheral device.

    摘要翻译： 系统的实施例包括容纳一个或多个能够与诸如RFID标签读取器的手持式计算设备一起使用的外围设备（例如无线电设备）的胶囊。 插座可以安装在手持式计算设备上。 容器接收胶囊。 当插座被插座接收时，胶囊和插座上的电连接器配合，以电连接外围设备和手持计算设备。 提供密封以防止水，灰尘和其他污染物渗入电连接器中。 当胶囊位于容器中时，胶囊的一部分被暴露，以容纳外围设备可能需要的外部天线，连接器，光学端口等。

    Integrated circuit with depletion mode JFET
    2.
    发明申请
    Integrated circuit with depletion mode JFET 失效
    具有耗尽型JFET的集成电路

    公开(公告)号：US20070069250A1

    公开(公告)日：2007-03-29

    申请号：US11237095

    申请日：2005-09-28

    申请人： Alan Chen ,  Daniel Dolan ,  David Kelly ,  Daniel Kerr ,  Stephen Kuehne

    发明人： Alan Chen ,  Daniel Dolan ,  David Kelly ,  Daniel Kerr ,  Stephen Kuehne

    IPC分类号： H01L29/80

    CPC分类号： H01L29/808 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/098 ,  H01L29/1066 ,  H01L29/7833

    摘要： An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device. P-type dopant is introduced into the semiconductor layer to simultaneously form a higher concentration p-type region in the p-well of the NMOS device and a channel region extending between the source and drain of the JFET.

    摘要翻译： 具有n沟道MOSFET器件和JFET器件的集成电路。 集成电路包括具有上表面的半导体层，形成在从半导体上表面延伸的第一导电类型的掺杂阱中的MOS晶体管器件和JFET器件。 JFET器件包括半导体层中的与上表面间隔开并具有位于预定距离的峰值浓度的沟道区域。 相关联的制造方法包括将p型掺杂剂引入半导体表面以形成其中形成NMOS器件的p阱以及JFET器件的源极和漏极。 N型掺杂剂被引入到半导体表面中以在p阱的下面形成NMOS器件的n型区域和JFET器件的栅极区域。 P型掺杂剂被引入到半导体层中，以在NMOS器件的p阱和在JFET的源极和漏极之间延伸的沟道区域中同时形成更高浓度的p型区域。